library IEEE;
use IEEE.std_logic_1164.all;
use WORK.RECV_PACKAGE.all;

entity recv_top is

  generic(
     
	DATA_BIT : integer := 64;                  -- 數(shù)據(jù)位個(gè)數(shù)
	TOTAL_BIT : integer := 66                -- 總數(shù)據(jù)個(gè)數(shù)
  );
  port(
	  
       clk : in STD_LOGIC;               -- 時(shí)鐘信號(hào)
       wrfull: in std_logic;             --fifo 滿標(biāo)志
	   wrclk : out std_logic;            --提供給fifo的寫時(shí)鐘
 --      error : out STD_LOGIC;            -- 錯(cuò)誤提示信號(hào)
       wrreq : out STD_LOGIC;            -- 接收提示信號(hào)
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);-- 數(shù)據(jù)接收總線
       TxD : out std_logic;
       RxD : in STD_LOGIC );               -- RS-232數(shù)據(jù)接收端口
end recv_top;

architecture recv_top of recv_top is

-- 計(jì)數(shù)器組件聲明
component counter
  generic(
       MAX_COUNT : INTEGER := 66
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       overflow : out STD_LOGIC
  );
end component;
-- 信號(hào)監(jiān)測(cè)器
component detector
  port (
       RxD : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       new_data : out STD_LOGIC
  );
end component;
--奇偶校驗(yàn)
component parity_verifier1 is
	-- 類屬參數(shù)
	generic (
	DATA_LENGTH : integer := 64;
	PARITY_RULE : PARITY := ODD );
	-- 端口
	port (
	source : in std_logic_vector(DATA_LENGTH-1 downto 0);
	parity : out std_logic );
end component;

-- 移位寄存器
component shift_register1
  generic(
       TOTAL_BIT : INTEGER := 69
  );
  port (
       clk : in STD_LOGIC;
       din : in STD_LOGIC;
       reset_n : in STD_LOGIC;
     --  dout : out STD_LOGIC;
       regs : out STD_LOGIC_VECTOR(TOTAL_BIT-1 downto 0)
  );
end component;
--TxD輸出選擇器
component switch2 is
  port (
       din1 : in STD_LOGIC;
       din2 : in STD_LOGIC;
       sel : in STD_LOGIC;
       dout : out STD_LOGIC
  );
end component;

-- UART內(nèi)核
component recv_core
  generic(
       DATA_BIT : INTEGER := DATA_BIT;
       TOTAL_BIT : INTEGER := TOTAL_BIT;

       PARITY_RULE:PARITY:=ODD
  );
  port (
       clk : in STD_LOGIC;
	   wrclk : out std_logic;
	   wrfull: in std_logic;
       new_data : in STD_LOGIC;
       overflow : in STD_LOGIC;
       regs : in STD_LOGIC_VECTOR(68 downto 0);
       ce_parts : out STD_LOGIC;
	   sel_TxD:out std_logic;
       parity:in std_logic;
       wrreq : out STD_LOGIC;
       TxD : out std_logic;
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
       pv_in:out std_logic_vector(DATA_BIT-1 downto 0);
       reset_dt : out STD_LOGIC;     	
       reset_shift:out std_logic;
       reset_parts : out STD_LOGIC
       
  );
end component;

constant VCC_CONSTANT   : STD_LOGIC := '1';
---- 內(nèi)部信號(hào)聲明 ----
signal VCC : STD_LOGIC;
signal ce_parts : STD_LOGIC;
signal new_data : STD_LOGIC;
signal overflow : STD_LOGIC;
signal reset_dt : STD_LOGIC;
signal reset_parts : STD_LOGIC;
signal reset_shift:std_logic;
signal regs : STD_LOGIC_VECTOR (68 downto 0);
signal pv : std_logic;
signal pv_in:std_logic_vector(63 downto 0);
signal sel_TxD:std_logic;
signal TxD_core:std_logic;

begin

	VCC <= VCC_CONSTANT;   

	-- UART內(nèi)核實(shí)例
	U_Core1 : recv_core
	  port map(
	       ce_parts => ce_parts,
	       clk => clk,
	       wrclk =>wrclk,
	       wrfull =>wrfull,
	       new_data => new_data,
	       overflow => overflow,
	       wrreq => wrreq,
	       TxD => TxD_core,
	       sel_TxD => sel_TxD,
	       parity => pv,
	       recv_bus => recv_bus,
	       regs => regs( 68 downto 0 ),
	       reset_dt => reset_dt,
	       pv_in => pv_in,
	       reset_shift =>reset_shift,
	       reset_parts => reset_parts
	  );
	-- 計(jì)數(shù)器實(shí)例
	U_Counter1 : counter
	  port map(
	       ce => ce_parts,
	       clk => clk,
	       overflow => overflow,
	       reset_n => reset_parts
	  );
	-- 信號(hào)監(jiān)測(cè)器
	U_Detector1 : detector
	  port map(
	       RxD => RxD,
	       clk => clk,
	       new_data => new_data,
	       reset_n => reset_dt
	  );
	-- 移位寄存器實(shí)例
	U_SR1 : shift_register1
	  port map(
	       clk => clk,
	       din => RxD,
	       regs => regs( 68 downto 0 ),
	       reset_n => reset_shift
	  );
    U_PV1:parity_verifier1
       port map(
           source => pv_in,
           parity => pv
      );
     U_sw:switch2
       port map( 
           din1 => VCC,
           din2 => TxD_core,
           sel => sel_TxD,
           dout => TxD
      );  
end recv_top;