-- 庫聲明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.RECV_PACKAGE.all;

entity recv_core is
	generic (
	
	DATA_BIT : integer := 64;-- 數(shù)據(jù)位個(gè)數(shù)
	TOTAL_BIT : integer := 66;-- 總數(shù)據(jù)個(gè)數(shù)
    PARITY_RULE:PARITY:=ODD
    );
	port (
	-- 時(shí)鐘和復(fù)位信號(hào)
	clk : in std_logic;
	-- 和信號(hào)監(jiān)測(cè)器的接口信號(hào)
	new_data : in std_logic;
	reset_dt : out std_logic;
	-- 復(fù)位、使能子模塊的信號(hào)
	reset_parts : out std_logic;
	reset_shift:out std_logic;
	ce_parts : out std_logic;
	parity:in std_logic;
	sel_TxD:out std_logic;
	-- 和移位寄存器的接口信號(hào)
	regs : in std_logic_vector(68 downto 0);
	-- 計(jì)數(shù)器時(shí)鐘選擇信號(hào)和計(jì)數(shù)器計(jì)數(shù)到達(dá)上閾的指示信號(hào)
	overflow : in std_logic;
	-- 提供給CPU的接口信號(hào)
	wrfull: in std_logic;
	wrreq : out std_logic;
	wrclk : out std_logic;
	TxD  : out std_logic;
	pv_in:out std_logic_vector(DATA_BIT-1 downto 0);
	recv_bus : out std_logic_vector(DATA_BIT-1 downto 0)
	 );
	
end recv_core;


architecture recv_core of recv_core is

-- 內(nèi)部信號(hào)
signal state : UART_STATE := UART_IDLE;
signal reg:std_logic;
signal reg4:std_logic_vector(5 downto 0);
signal count1:integer;
signal error :std_logic;
signal full:std_logic := '0';

begin
    wrclk <= clk;
	-- 主過程
	main: process(clk)
	begin
        if rising_edge(clk) then
		      case state is
		    	when UART_IDLE =>      -- 空閑狀態(tài)
		        if wrfull='1' then
		              full <= wrfull;
					  count1 <= 0;
		              state <= SEND_BACK;
		        else 		            
		     		if new_data = '1' then -- 當(dāng)信號(hào)監(jiān)測(cè)器監(jiān)測(cè)到數(shù)據(jù)時(shí)，new_data變?yōu)?#039;1'
		    			reset_parts <= '0';-- 復(fù)位子模塊
		   	    		ce_parts <= '0';   -- 子模塊使能無效
		   	    		reset_shift <= '1';
		                sel_TxD <= '0';
		                error <= '0';
		                wrreq <= '0';
		   	    		state <= UART_RECV;-- 改變狀態(tài)為接收
		   	    	else	
		    	        sel_TxD <= '0';
                        error <= '0';
		    	        wrreq <= '0';
		    	        reset_dt <= '1';   -- 停止對(duì)信號(hào)監(jiān)測(cè)器的復(fù)位
		    		end if;
               end if; 
				-------- 數(shù)據(jù)接收狀態(tài)--------
				-- 接收狀態(tài)
				when UART_RECV =>
				
				if overflow = '1' then     -- 如果overflow變?yōu)?quot;1"，表示接收完成
					reg <= regs(65);
					recv_bus <= regs(DATA_BIT downto 1);-- 總線數(shù)據(jù)輸出
					pv_in <= regs(DATA_BIT downto 1);
					state <= UART_END_RECV;-- 改變狀態(tài)為接收完成
				else
					reset_parts <= '1';    -- 子模塊復(fù)位信號(hào)無效
					ce_parts <= '1';       -- 子模塊使能信號(hào)有效
					reset_shift <= '1';
				end if;
				
				-- 接收完成狀態(tài)
				when UART_END_RECV =>
				
				if not( reg = parity) then
				    error <= '1';
				else
					wrreq <= '1';		   -- 輸出接收指示信號(hào)  
				end if;
				ce_parts <= '0';              -- 子模塊使能信號(hào)無效
				count1 <= 0;
				state <= SEND_BACK;           -- 改變狀態(tài)為空閑
				
				when SEND_BACK =>
				    if not(count1 = 6) then
		        	   sel_TxD <= '1';
                       TxD <= reg4(5- count1);
                       count1 <= count1 +1;
                     else
                        sel_TxD <= '0';
                        full <= '0';
 	        			reset_dt <= '0';              -- 復(fù)位信號(hào)監(jiān)測(cè)器
                        state <= UART_IDLE;
                    end if;
                   wrreq <= '0';

				when others =>                -- 如果產(chǎn)生未知狀態(tài)，輸出錯(cuò)誤信息
				error <= '1';
				state <= UART_IDLE;           -- 恢復(fù)到空閑狀態(tài)
			  end case;
		end if;
	end process;	
  ---------------------------   
    process (error, full)
    begin 
          if rising_edge(clk) then
              if error = '1' and full ='0' then      --發(fā)錯(cuò)
                 reg4 <= "000001";
              elsif error = '0' and full = '1' then   --fifo滿
                 reg4 <= "000010";
              else                        --正確
                 reg4 <= "000000";
              end if;
           end if;
    end process;
 
end recv_core;