?? fspi.tan.qmsg
字號:
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "fspi:inst\|clkout " "Info: Node \"fspi:inst\|clkout\"" { } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 11 -1 0 } } } 0} } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 11 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "fspi:inst\|fiforead " "Info: Node \"fspi:inst\|fiforead\"" { } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 11 -1 0 } } } 0} } { { "Fspi.vhd" "" { Text "D:/spi/send/spi backup/Fspi/Fspi.vhd" 11 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "spiclk " "Info: Assuming node \"spiclk\" is an undefined clock" { } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 288 208 376 304 "spiclk" "" } { 280 392 584 296 "spiclk" "" } { 120 280 328 136 "spiclk" "" } { 104 280 328 120 "spiclk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "spiclk" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "syn_in " "Info: Assuming node \"syn_in\" is an undefined clock" { } { { "spi.bdf" "" { Schematic "D:/spi/send/spi backup/Fspi/spi.bdf" { { 1032 120 288 1048 "syn_in" "" } { 1024 288 344 1040 "syn_in" "" } { 1520 752 840 1536 "syn_in" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "syn_in" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" { } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } } } 0} } { } 0}
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