--dffpipe DELAY=3 WIDTH=8 clock clrn d q
--VERSION_BEGIN 5.0 cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 24 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_3a3
( 
	clock	:	input;
	clrn	:	input;
	d[7..0]	:	input;
	q[7..0]	:	output;
) 
VARIABLE 
	dffe15a[7..0] : dffe;
	dffe16a[7..0] : dffe;
	dffe17a[7..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe15a[].CLK = clock;
	dffe15a[].CLRN = clrn;
	dffe15a[].D = (d[] & (! sclr));
	dffe15a[].ENA = ena;
	dffe15a[].PRN = prn;
	dffe16a[].CLK = clock;
	dffe16a[].CLRN = clrn;
	dffe16a[].D = (dffe15a[].Q & (! sclr));
	dffe16a[].ENA = ena;
	dffe16a[].PRN = prn;
	dffe17a[].CLK = clock;
	dffe17a[].CLRN = clrn;
	dffe17a[].D = (dffe16a[].Q & (! sclr));
	dffe17a[].ENA = ena;
	dffe17a[].PRN = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe17a[].Q;
	sclr = GND;
END;
--VALID FILE