?? outtest.vhd
字號(hào):
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity outtest is
port(wrreq,wrclk:out std_logic;
wrfull:in std_logic;
testdata:out std_logic_vector(63 downto 0));
end outtest;
architecture rtl of outtest is
begin
process
begin
if(wrfull='0') then
wrreq<='1';
wrclk<='1';
testdata<="1000100010001000011101110111011101100110011001100101010101010101";
end if;
end process;
end rtl;
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