/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/
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	(text "inst" (rect 8 80 25 92)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "wrfull" (rect 0 0 25 12)(font "Arial" ))
		(text "wrfull" (rect 21 27 46 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
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	(port
		(pt 152 32)
		(output)
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		(text "wrreq" (rect 106 27 131 39)(font "Arial" ))
		(line (pt 152 32)(pt 136 32)(line_width 1))
	)
	(port
		(pt 152 48)
		(output)
		(text "wrclk" (rect 0 0 24 12)(font "Arial" ))
		(text "wrclk" (rect 107 43 131 55)(font "Arial" ))
		(line (pt 152 48)(pt 136 48)(line_width 1))
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	(port
		(pt 152 64)
		(output)
		(text "testdata[63..0]" (rect 0 0 71 12)(font "Arial" ))
		(text "testdata[63..0]" (rect 60 59 131 71)(font "Arial" ))
		(line (pt 152 64)(pt 136 64)(line_width 3))
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	(drawing
		(rectangle (rect 16 16 136 80)(line_width 1))
	)
)