{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rdclk " "Info: Destination \"rdclk\" may be non-global or may not use global clock" {  } { { "send_top.vhd" "" { Text "E:/課題/預警/send/send_top.vhd" 14 -1 0 } }  } 0}  } { { "send_top.vhd" "" { Text "E:/課題/預警/send/send_top.vhd" 13 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "send_core:U_Core\|reset_parts Global clock " "Info: Automatically promoted some destinations of signal \"send_core:U_Core\|reset_parts\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|altsyncram_0uu:altsyncram2\|ram_block3a0 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|altsyncram_0uu:altsyncram2\|ram_block3a0\" may be non-global or may not use global clock" {  } { { "db/altsyncram_0uu.tdf" "" { Text "E:/課題/預警/send/db/altsyncram_0uu.tdf" 45 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella0 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella0\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella1 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella1\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella2 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella2\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella3 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella3\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella4 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella4\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella5 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella5\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella6 " "Info: Destination \"shift_register:U_SR\|altshift_taps:shift_regs_rtl_0\|shift_taps_s5h:auto_generated\|cntr_tgc:cntr1\|counter_cella6\" may be non-global or may not use global clock" {  } { { "db/cntr_tgc.tdf" "" { Text "E:/課題/預警/send/db/cntr_tgc.tdf" 108 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "send_core:U_Core\|Select~1558 " "Info: Destination \"send_core:U_Core\|Select~1558\" may be non-global or may not use global clock" {  } {  } 0}  } { { "send_core.vhd" "" { Text "E:/課題/預警/send/send_core.vhd" 20 -1 0 } }  } 0}