--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" NUMBER_OF_TAPS=1 TAP_DISTANCE=65 WIDTH=1 clken clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.0 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altshift_taps 2004:12:13:14:36:10:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_qtu (address_a[5..0], address_b[5..0], clock0, clocken0, data_a[0..0], wren_a)
RETURNS ( q_b[0..0]);
FUNCTION cntr_qgc (clk_en, clock)
RETURNS ( q[5..0]);

--synthesis_resources = lut 11 M4K 1 
SUBDESIGN shift_taps_q5h
( 
	clken	:	input;
	clock	:	input;
	shiftin[0..0]	:	input;
	shiftout[0..0]	:	output;
	taps[0..0]	:	output;
) 
VARIABLE 
	altsyncram2 : altsyncram_qtu;
	cntr1 : cntr_qgc;

BEGIN 
	altsyncram2.address_a[] = cntr1.q[];
	altsyncram2.address_b[] = cntr1.q[];
	altsyncram2.clock0 = clock;
	altsyncram2.clocken0 = clken;
	altsyncram2.data_a[] = ( shiftin[]);
	altsyncram2.wren_a = B"1";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	shiftout[0..0] = altsyncram2.q_b[0..0];
	taps[] = altsyncram2.q_b[];
END;
--VALID FILE