Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1614
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
switch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
switch.vhd
1145581157
4
# storage
db|send.(4).cnf
db|send.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
switch:U_TXDSwitch
}
# end
# entity
altshift_taps
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altshift_taps.tdf
1114012440
6
# storage
db|send.(6).cnf
db|send.(6).cnf
# user_parameter {
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
66
PARAMETER_UNKNOWN
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_r5h
PARAMETER_UNKNOWN
USR
}
# used_port {
clken
clock
shiftin0
taps0
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
d:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
d:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
shift_taps_r5h
# case_insensitive
# source_file
db|shift_taps_r5h.tdf
1145607687
6
# storage
db|send.(7).cnf
db|send.(7).cnf
# used_port {
shiftin0
clock
clken
taps0
}
# end
# entity
cntr_rgc
# case_insensitive
# source_file
db|cntr_rgc.tdf
1145607687
6
# storage
db|send.(9).cnf
db|send.(9).cnf
# used_port {
clk_en
clock
q0
q1
q2
q3
q4
q5
}
# end
# entity
crc
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
crc.vhd
1146191681
4
# storage
db|send.(5).cnf
db|send.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
altshift_taps
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altshift_taps.tdf
1114012440
6
# storage
db|send.(8).cnf
db|send.(8).cnf
# user_parameter {
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
70
PARAMETER_UNKNOWN
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_m5h
PARAMETER_UNKNOWN
USR
}
# used_port {
clken
clock
shiftin0
taps0
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
d:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
d:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
shift_taps_m5h
# case_insensitive
# source_file
db|shift_taps_m5h.tdf
1146191693
6
# storage
db|send.(10).cnf
db|send.(10).cnf
# used_port {
shiftin0
clock
clken
taps0
}
# end
# entity
cntr_0hc
# case_insensitive
# source_file
db|cntr_0hc.tdf
1146191693
6
# storage
db|send.(12).cnf
db|send.(12).cnf
# used_port {
clk_en
clock
q0
q1
q2
q3
q4
q5
q6
}
# end
# entity
altshift_taps
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altshift_taps.tdf
1114012440
6
# storage
db|send.(11).cnf
db|send.(11).cnf
# user_parameter {
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
66
PARAMETER_UNKNOWN
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_3ng
PARAMETER_UNKNOWN
USR
}
# used_port {
clken
clock
shiftin0
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
d:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
d:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
shift_taps_3ng
# case_insensitive
# source_file
db|shift_taps_3ng.tdf
1146279672
6
# storage
db|send.(13).cnf
db|send.(13).cnf
# used_port {
shiftin0
clock
clken
}
# end
# entity
send
# case_insensitive
# source_file
send.bdf
1146287972
23
# storage
db|send.(14).cnf
db|send.(14).cnf
# end
# entity
altshift_taps
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altshift_taps.tdf
1114012440
6
# storage
db|send.(16).cnf
db|send.(16).cnf
# user_parameter {
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
65
PARAMETER_UNKNOWN
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_q5h
PARAMETER_UNKNOWN
USR
}
# used_port {
clken
clock
shiftin0
taps0
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
d:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
d:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
shift_taps_q5h
# case_insensitive
# source_file
db|shift_taps_q5h.tdf
1147917120
6
# storage
db|send.(17).cnf
db|send.(17).cnf
# used_port {
shiftin0
clock
clken
taps0
}
# end
# entity
cntr_qgc
# case_insensitive
# source_file
db|cntr_qgc.tdf
1147917119
6
# storage
db|send.(19).cnf
db|send.(19).cnf
# used_port {
clk_en
clock
q0
q1
q2
q3
q4
q5
}
# end
# entity
parity_verifier
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
parity_verifier.vhd
1148020809
4
# storage
db|send.(15).cnf
db|send.(15).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
data_length
64
PARAMETER_DEC
USR
parity_rule
ODD
PARAMETER_ENUM
USR
}
# include_file {
send_package.vhd
1148030506
}
# hierarchies {
parity_verifier:U_PV
}
# end
# entity
detector1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
detector1.vhd
1147956746
4
# storage
db|send.(18).cnf
db|send.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
send_package.vhd
1148030506
}
# hierarchies {
detector1:U_detector
}
# end
# entity
counter
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
counter.vhd
1148098514
4
# storage
db|send.(2).cnf
db|send.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
max_count
66
PARAMETER_DEC
USR
}
# hierarchies {
counter:U_Counter
}
# end
# entity
shift_register
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
shift_register.vhd
1148098515
4
# storage
db|send.(3).cnf
db|send.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
total_bit
67
PARAMETER_DEC
USR
}
# hierarchies {
shift_register:U_SR
}
# end
# entity
altshift_taps
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altshift_taps.tdf
1114012440
6
# storage
db|send.(20).cnf
db|send.(20).cnf
# user_parameter {
NUMBER_OF_TAPS
1
PARAMETER_UNKNOWN
USR
TAP_DISTANCE
67
PARAMETER_UNKNOWN
USR
WIDTH
1
PARAMETER_UNKNOWN
USR
POWER_UP_STATE
CLEARED
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
shift_taps_s5h
PARAMETER_UNKNOWN
USR
}
# used_port {
clken
clock
shiftin0
taps0
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|lpm_counter.inc
1107574548
d:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
d:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
shift_taps_s5h
# case_insensitive
# source_file
db|shift_taps_s5h.tdf
1148098555
6
# storage
db|send.(21).cnf
db|send.(21).cnf
# used_port {
shiftin0
clock
clken
taps0
}
# end
# entity
cntr_tgc
# case_insensitive
# source_file
db|cntr_tgc.tdf
1148098555
6
# storage
db|send.(23).cnf
db|send.(23).cnf
# used_port {
clk_en
clock
q0
q1
q2
q3
q4
q5
q6
}
# end
# entity
send_core
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
send_core.vhd
1148268092
4
# storage
db|send.(1).cnf
db|send.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
data_bit
64
PARAMETER_DEC
USR
total_bit
66
PARAMETER_DEC
USR
parity_rule
ODD
PARAMETER_ENUM
USR
}
# include_file {
send_package.vhd
1148030506
}
# hierarchies {
send_core:U_Core
}
# end
# entity
send_top
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
send_top.vhd
1148281669
4
# storage
db|send.(0).cnf
db|send.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
data_bit
64
PARAMETER_DEC
DEF
total_bit
66
PARAMETER_DEC
DEF
}
# include_file {
send_package.vhd
1148030506
}
# hierarchies {
|
}
# end
# entity
altsyncram_0uu
# case_insensitive
# source_file
db|altsyncram_0uu.tdf
1148098555
6
# storage
db|send.(22).cnf
db|send.(22).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
clock0
clocken0
data_a0
wren_a
q_b0
}
# memory_file {
none
0
}
# end
# complete