?? bjq.tan.rpt
字號(hào):
Timing Analyzer report for bjq
Fri Jun 09 11:18:33 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.150 ns ; rd ; ed[3] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------------+--------+
; N/A ; None ; 16.150 ns ; rd ; ed[3] ;
; N/A ; None ; 16.042 ns ; rd ; ed[7] ;
; N/A ; None ; 15.949 ns ; rd ; ed[8] ;
; N/A ; None ; 15.887 ns ; rd ; ed[13] ;
; N/A ; None ; 15.884 ns ; rd ; ed[12] ;
; N/A ; None ; 15.864 ns ; rd ; ed[4] ;
; N/A ; None ; 15.835 ns ; rd ; ed[9] ;
; N/A ; None ; 15.827 ns ; rd ; ed[10] ;
; N/A ; None ; 15.780 ns ; ce ; ed[3] ;
; N/A ; None ; 15.777 ns ; rd ; ed[2] ;
; N/A ; None ; 15.742 ns ; rd ; ed[14] ;
; N/A ; None ; 15.739 ns ; rd ; ed[0] ;
; N/A ; None ; 15.728 ns ; rd ; ed[11] ;
; N/A ; None ; 15.727 ns ; rd ; ed[6] ;
; N/A ; None ; 15.693 ns ; rd ; ed[15] ;
; N/A ; None ; 15.693 ns ; rd ; ed[5] ;
; N/A ; None ; 15.693 ns ; rd ; ed[1] ;
; N/A ; None ; 15.672 ns ; ce ; ed[7] ;
; N/A ; None ; 15.579 ns ; ce ; ed[8] ;
; N/A ; None ; 15.517 ns ; ce ; ed[13] ;
; N/A ; None ; 15.514 ns ; ce ; ed[12] ;
; N/A ; None ; 15.494 ns ; ce ; ed[4] ;
; N/A ; None ; 15.465 ns ; ce ; ed[9] ;
; N/A ; None ; 15.457 ns ; ce ; ed[10] ;
; N/A ; None ; 15.407 ns ; ce ; ed[2] ;
; N/A ; None ; 15.372 ns ; ce ; ed[14] ;
; N/A ; None ; 15.369 ns ; ce ; ed[0] ;
; N/A ; None ; 15.358 ns ; ce ; ed[11] ;
; N/A ; None ; 15.357 ns ; ce ; ed[6] ;
; N/A ; None ; 15.323 ns ; ce ; ed[15] ;
; N/A ; None ; 15.323 ns ; ce ; ed[5] ;
; N/A ; None ; 15.323 ns ; ce ; ed[1] ;
; N/A ; None ; 10.733 ns ; dfftodsp0[3] ; ed[3] ;
; N/A ; None ; 10.427 ns ; dfftodsp0[12] ; ed[12] ;
; N/A ; None ; 10.421 ns ; dfftodsp0[9] ; ed[9] ;
; N/A ; None ; 10.421 ns ; dfftodsp0[4] ; ed[4] ;
; N/A ; None ; 10.419 ns ; dfftodsp0[10] ; ed[10] ;
; N/A ; None ; 10.310 ns ; dfftodsp0[8] ; ed[8] ;
; N/A ; None ; 10.301 ns ; dfftodsp0[13] ; ed[13] ;
; N/A ; None ; 10.053 ns ; dfftodsp0[0] ; ed[0] ;
; N/A ; None ; 9.966 ns ; dfftodsp0[15] ; ed[15] ;
; N/A ; None ; 9.661 ns ; dfftodsp0[5] ; ed[5] ;
; N/A ; None ; 9.661 ns ; dfftodsp0[1] ; ed[1] ;
; N/A ; None ; 9.656 ns ; dfftodsp0[14] ; ed[14] ;
; N/A ; None ; 9.647 ns ; dfftodsp0[11] ; ed[11] ;
; N/A ; None ; 9.645 ns ; dfftodsp0[2] ; ed[2] ;
; N/A ; None ; 7.243 ns ; dfftodsp0[7] ; ed[7] ;
; N/A ; None ; 7.114 ns ; dfftodsp0[6] ; ed[6] ;
+-------+-------------------+-----------------+---------------+--------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Fri Jun 09 11:18:32 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bjq -c bjq --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "ed[0]$latch" is a latch
Warning: Node "ed[1]$latch" is a latch
Warning: Node "ed[2]$latch" is a latch
Warning: Node "ed[3]$latch" is a latch
Warning: Node "ed[4]$latch" is a latch
Warning: Node "ed[5]$latch" is a latch
Warning: Node "ed[6]$latch" is a latch
Warning: Node "ed[7]$latch" is a latch
Warning: Node "ed[8]$latch" is a latch
Warning: Node "ed[9]$latch" is a latch
Warning: Node "ed[10]$latch" is a latch
Warning: Node "ed[11]$latch" is a latch
Warning: Node "ed[12]$latch" is a latch
Warning: Node "ed[13]$latch" is a latch
Warning: Node "ed[14]$latch" is a latch
Warning: Node "ed[15]$latch" is a latch
Info: Found combinational loop of 1 nodes
Info: Node "ed[15]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[14]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[13]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[12]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[11]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[10]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[9]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[8]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[7]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[6]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[5]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[4]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[3]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[2]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[1]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "ed[0]$latch"
Info: Longest tpd from source pin "rd" to destination pin "ed[3]" is 16.150 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'rd'
Info: 2: + IC(5.786 ns) + CELL(0.292 ns) = 7.553 ns; Loc. = LC_X6_Y9_N2; Fanout = 32; COMB Node = 'a~0'
Info: 3: + IC(0.000 ns) + CELL(4.941 ns) = 12.494 ns; Loc. = LC_X9_Y1_N2; Fanout = 2; COMB LOOP Node = 'ed[3]$latch'
Info: Loc. = LC_X9_Y1_N2; Node "ed[3]$latch"
Info: 4: + IC(1.548 ns) + CELL(2.108 ns) = 16.150 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'ed[3]'
Info: Total cell delay = 8.816 ns ( 54.59 % )
Info: Total interconnect delay = 7.334 ns ( 45.41 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 17 warnings
Info: Processing ended: Fri Jun 09 11:18:33 2006
Info: Elapsed time: 00:00:01
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