?? cce.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cce is
port(ds,ps:in std_logic;
ce:out std_logic);
end cce;
architecture bhv of cce is
begin
process(ds,ps)
begin
if((ds='0') and (ps='0'))then
ce<='0';
elSE
ce<='1';
end if;
end process;
end bhv;
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