?? fpgawrite.tan.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 09 10:34:10 2006 " "Info: Processing started: Fri Jun 09 10:34:10 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fpgawrite -c fpgawrite --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fpgawrite -c fpgawrite --timing_analysis_only" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "fpgawrite.vhd" "" { Text "E:/gytask/fpgawrite1/fpgawrite.vhd" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" { } { } 0}
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