{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register recv_core:U_Core1\|count1\[6\] register recv_core:U_Core1\|reset_dt 120.98 MHz 8.266 ns Internal " "Info: Clock \"clk\" has Internal fmax of 120.98 MHz between source register \"recv_core:U_Core1\|count1\[6\]\" and destination register \"recv_core:U_Core1\|reset_dt\" (period= 8.266 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.005 ns + Longest register register " "Info: + Longest register to register delay is 8.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns recv_core:U_Core1\|count1\[6\] 1 REG LC_X21_Y10_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N0; Fanout = 4; REG Node = 'recv_core:U_Core1\|count1\[6\]'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { recv_core:U_Core1|count1[6] } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.590 ns) 1.859 ns recv_core:U_Core1\|reduce_nor~296 2 COMB LC_X21_Y11_N0 1 " "Info: 2: + IC(1.269 ns) + CELL(0.590 ns) = 1.859 ns; Loc. = LC_X21_Y11_N0; Fanout = 1; COMB Node = 'recv_core:U_Core1\|reduce_nor~296'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.859 ns" { recv_core:U_Core1|count1[6] recv_core:U_Core1|reduce_nor~296 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.292 ns) 3.319 ns recv_core:U_Core1\|reduce_nor~299 3 COMB LC_X20_Y11_N2 1 " "Info: 3: + IC(1.168 ns) + CELL(0.292 ns) = 3.319 ns; Loc. = LC_X20_Y11_N2; Fanout = 1; COMB Node = 'recv_core:U_Core1\|reduce_nor~299'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.460 ns" { recv_core:U_Core1|reduce_nor~296 recv_core:U_Core1|reduce_nor~299 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.292 ns) 4.072 ns recv_core:U_Core1\|reduce_nor~0 4 COMB LC_X20_Y11_N7 7 " "Info: 4: + IC(0.461 ns) + CELL(0.292 ns) = 4.072 ns; Loc. = LC_X20_Y11_N7; Fanout = 7; COMB Node = 'recv_core:U_Core1\|reduce_nor~0'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "0.753 ns" { recv_core:U_Core1|reduce_nor~299 recv_core:U_Core1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.479 ns) + CELL(0.292 ns) 4.843 ns recv_core:U_Core1\|Select~884 5 COMB LC_X20_Y11_N9 3 " "Info: 5: + IC(0.479 ns) + CELL(0.292 ns) = 4.843 ns; Loc. = LC_X20_Y11_N9; Fanout = 3; COMB Node = 'recv_core:U_Core1\|Select~884'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "0.771 ns" { recv_core:U_Core1|reduce_nor~0 recv_core:U_Core1|Select~884 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.590 ns) 6.666 ns recv_core:U_Core1\|Select~890 6 COMB LC_X19_Y10_N7 1 " "Info: 6: + IC(1.233 ns) + CELL(0.590 ns) = 6.666 ns; Loc. = LC_X19_Y10_N7; Fanout = 1; COMB Node = 'recv_core:U_Core1\|Select~890'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.823 ns" { recv_core:U_Core1|Select~884 recv_core:U_Core1|Select~890 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.867 ns) 8.005 ns recv_core:U_Core1\|reset_dt 7 REG LC_X19_Y10_N6 2 " "Info: 7: + IC(0.472 ns) + CELL(0.867 ns) = 8.005 ns; Loc. = LC_X19_Y10_N6; Fanout = 2; REG Node = 'recv_core:U_Core1\|reset_dt'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.339 ns" { recv_core:U_Core1|Select~890 recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.923 ns 36.51 % " "Info: Total cell delay = 2.923 ns ( 36.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.082 ns 63.49 % " "Info: Total interconnect delay = 5.082 ns ( 63.49 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "8.005 ns" { recv_core:U_Core1|count1[6] recv_core:U_Core1|reduce_nor~296 recv_core:U_Core1|reduce_nor~299 recv_core:U_Core1|reduce_nor~0 recv_core:U_Core1|Select~884 recv_core:U_Core1|Select~890 recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.005 ns" { recv_core:U_Core1|count1[6] recv_core:U_Core1|reduce_nor~296 recv_core:U_Core1|reduce_nor~299 recv_core:U_Core1|reduce_nor~0 recv_core:U_Core1|Select~884 recv_core:U_Core1|Select~890 recv_core:U_Core1|reset_dt } { 0.000ns 1.269ns 1.168ns 0.461ns 0.479ns 1.233ns 0.472ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.292ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns recv_core:U_Core1\|reset_dt 2 REG LC_X19_Y10_N6 2 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X19_Y10_N6; Fanout = 2; REG Node = 'recv_core:U_Core1\|reset_dt'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.473 ns" { clk recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.10 % " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns 25.90 % " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|reset_dt } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns recv_core:U_Core1\|count1\[6\] 2 REG LC_X21_Y10_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y10_N0; Fanout = 4; REG Node = 'recv_core:U_Core1\|count1\[6\]'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.473 ns" { clk recv_core:U_Core1|count1[6] } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.10 % " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns 25.90 % " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|count1[6] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|reset_dt } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|count1[6] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 18 -1 0 } }  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "8.005 ns" { recv_core:U_Core1|count1[6] recv_core:U_Core1|reduce_nor~296 recv_core:U_Core1|reduce_nor~299 recv_core:U_Core1|reduce_nor~0 recv_core:U_Core1|Select~884 recv_core:U_Core1|Select~890 recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.005 ns" { recv_core:U_Core1|count1[6] recv_core:U_Core1|reduce_nor~296 recv_core:U_Core1|reduce_nor~299 recv_core:U_Core1|reduce_nor~0 recv_core:U_Core1|Select~884 recv_core:U_Core1|Select~890 recv_core:U_Core1|reset_dt } { 0.000ns 1.269ns 1.168ns 0.461ns 0.479ns 1.233ns 0.472ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.292ns 0.590ns 0.867ns } } } { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|reset_dt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|reset_dt } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|count1[6] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "recv_core:U_Core1\|reset_parts wrfull clk 8.516 ns register " "Info: tsu for register \"recv_core:U_Core1\|reset_parts\" (data pin = \"wrfull\", clock pin = \"clk\") is 8.516 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.404 ns + Longest pin register " "Info: + Longest pin to register delay is 11.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wrfull 1 PIN PIN_98 12 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_98; Fanout = 12; PIN Node = 'wrfull'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { wrfull } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.885 ns) + CELL(0.292 ns) 8.652 ns recv_core:U_Core1\|reset_shift~46 2 COMB LC_X19_Y10_N5 1 " "Info: 2: + IC(6.885 ns) + CELL(0.292 ns) = 8.652 ns; Loc. = LC_X19_Y10_N5; Fanout = 1; COMB Node = 'recv_core:U_Core1\|reset_shift~46'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "7.177 ns" { wrfull recv_core:U_Core1|reset_shift~46 } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.885 ns) + CELL(0.867 ns) 11.404 ns recv_core:U_Core1\|reset_parts 3 REG LC_X8_Y10_N2 33 " "Info: 3: + IC(1.885 ns) + CELL(0.867 ns) = 11.404 ns; Loc. = LC_X8_Y10_N2; Fanout = 33; REG Node = 'recv_core:U_Core1\|reset_parts'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.752 ns" { recv_core:U_Core1|reset_shift~46 recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns 23.10 % " "Info: Total cell delay = 2.634 ns ( 23.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.770 ns 76.90 % " "Info: Total interconnect delay = 8.770 ns ( 76.90 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "11.404 ns" { wrfull recv_core:U_Core1|reset_shift~46 recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.404 ns" { wrfull wrfull~out0 recv_core:U_Core1|reset_shift~46 recv_core:U_Core1|reset_parts } { 0.000ns 0.000ns 6.885ns 1.885ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns recv_core:U_Core1\|reset_parts 2 REG LC_X8_Y10_N2 33 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X8_Y10_N2; Fanout = 33; REG Node = 'recv_core:U_Core1\|reset_parts'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.456 ns" { clk recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.925 ns" { clk recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 recv_core:U_Core1|reset_parts } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "11.404 ns" { wrfull recv_core:U_Core1|reset_shift~46 recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.404 ns" { wrfull wrfull~out0 recv_core:U_Core1|reset_shift~46 recv_core:U_Core1|reset_parts } { 0.000ns 0.000ns 6.885ns 1.885ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.925 ns" { clk recv_core:U_Core1|reset_parts } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 recv_core:U_Core1|reset_parts } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk TxD recv_core:U_Core1\|TxD 8.774 ns register " "Info: tco from clock \"clk\" to destination pin \"TxD\" through register \"recv_core:U_Core1\|TxD\" is 8.774 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns recv_core:U_Core1\|TxD 2 REG LC_X21_Y11_N3 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y11_N3; Fanout = 1; REG Node = 'recv_core:U_Core1\|TxD'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.473 ns" { clk recv_core:U_Core1|TxD } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.10 % " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns 25.90 % " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|TxD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|TxD } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.608 ns + Longest register pin " "Info: + Longest register to pin delay is 5.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns recv_core:U_Core1\|TxD 1 REG LC_X21_Y11_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N3; Fanout = 1; REG Node = 'recv_core:U_Core1\|TxD'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { recv_core:U_Core1|TxD } "NODE_NAME" } "" } } { "recv_core.vhd" "" { Text "E:/課題/預警/recv/recv_core.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.590 ns) 1.356 ns switch2:U_sw\|dout~2 2 COMB LC_X22_Y11_N4 1 " "Info: 2: + IC(0.766 ns) + CELL(0.590 ns) = 1.356 ns; Loc. = LC_X22_Y11_N4; Fanout = 1; COMB Node = 'switch2:U_sw\|dout~2'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "1.356 ns" { recv_core:U_Core1|TxD switch2:U_sw|dout~2 } "NODE_NAME" } "" } } { "switch2.vhd" "" { Text "E:/課題/預警/recv/switch2.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.144 ns) + CELL(2.108 ns) 5.608 ns TxD 3 PIN PIN_205 0 " "Info: 3: + IC(2.144 ns) + CELL(2.108 ns) = 5.608 ns; Loc. = PIN_205; Fanout = 0; PIN Node = 'TxD'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "4.252 ns" { switch2:U_sw|dout~2 TxD } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns 48.11 % " "Info: Total cell delay = 2.698 ns ( 48.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.910 ns 51.89 % " "Info: Total interconnect delay = 2.910 ns ( 51.89 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "5.608 ns" { recv_core:U_Core1|TxD switch2:U_sw|dout~2 TxD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.608 ns" { recv_core:U_Core1|TxD switch2:U_sw|dout~2 TxD } { 0.000ns 0.766ns 2.144ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "2.942 ns" { clk recv_core:U_Core1|TxD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 recv_core:U_Core1|TxD } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "5.608 ns" { recv_core:U_Core1|TxD switch2:U_sw|dout~2 TxD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.608 ns" { recv_core:U_Core1|TxD switch2:U_sw|dout~2 TxD } { 0.000ns 0.766ns 2.144ns } { 0.000ns 0.590ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk wrclk 5.248 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"wrclk\" is 5.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 215 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 215; CLK Node = 'clk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "" { clk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(2.124 ns) 5.248 ns wrclk 2 PIN PIN_176 0 " "Info: 2: + IC(1.655 ns) + CELL(2.124 ns) = 5.248 ns; Loc. = PIN_176; Fanout = 0; PIN Node = 'wrclk'" {  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "3.779 ns" { clk wrclk } "NODE_NAME" } "" } } { "recv_top.vhd" "" { Text "E:/課題/預警/recv/recv_top.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns 68.46 % " "Info: Total cell delay = 3.593 ns ( 68.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.655 ns 31.54 % " "Info: Total interconnect delay = 1.655 ns ( 31.54 % )" {  } {  } 0}  } { { "E:/課題/預警/recv/db/recv_cmp.qrpt" "" { Report "E:/課題/預警/recv/db/recv_cmp.qrpt" Compiler "recv" "UNKNOWN" "V1" "E:/課題/預警/recv/db/recv.quartus_db" { Floorplan "E:/課題/預警/recv/" "" "5.248 ns" { clk wrclk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.248 ns" { clk clk~out0 wrclk } { 0.000ns 0.000ns 1.655ns } { 0.000ns 1.469ns 2.124ns } } }  } 0}