library verilog;use verilog.vl_types.all;entity uart_txd_vlg_sample_tst is    port(        clk_in          : in     vl_logic;        data_in         : in     vl_logic_vector(7 downto 0);        txd_en          : in     vl_logic;        sampler_tx      : out    vl_logic    );end uart_txd_vlg_sample_tst;