全加器仿真程序。

LIBRARY  IEEE;
USE  STD_TEXTIO.ALL;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_TEXTIO.ALL;
ENTITY test_fadder  IS 
END ENTITY test_fadder;
  
 ARCHITECTURE arc1 OF test_fadder IS
     COMPONENT f_adder IS
         PORT(ain,bin:IN STD_LOGIC;
               cin:IN STD_LOGIC;
              cout,sum:OUT STD_LOGIC );
     END COMPONENT f_adder;
FILE intest : TEXT  IS IN   "test1.in";
FILE outtest : TEXT  IS  OUT   "test1.out";

SIGNAL  test_ain,test_bin,test_cin : STD_LOGIC;
SIGNAL  test_co,test_s:STD_LOGIC;

BEGIN
U0: f_adder PORT MAP (ain=>test_ain ,bin=>test_bin,cin=>test_cin,
                     cout=>test_co,sum=>test_s); 
PROCESS
  VARIABLE li,ou:LINE;
  VARIABLE ain,bin,cin:STD_LOGIC;
  VARIABLE out_vector:STD_LOGIC(1 DOWNTO 0);
  BEGIN
     WHILE NOT ENDFILE (intest) LOOP
        READLINE (intest,li);
        READ(li,ain);
        READ(li,bin);
        READ(li,cin);
        test_ain<=ain;
        test_bin<=bin;
        test_cin<=cin;
WAIT FOR 20 ns; --  wait for circuit to settle
out_vector := sum & cout;
WRITE(ou,out_vector);
WRITELINE(outtest,ou);
WAIT FOR 80 ns; 
  END LOOP;
ASSERT FALSE REPORT “Test completed”;
  END PROCESS;
END  ARCHITECTURE arc1;