全加器仿真程序。

 LIBRARY  IEEE;
 USE  IEEE.STD_LOGIC_1164.ALL;
 ENTITY f_adder  IS
   PORT(
        ain,bin:IN STD_LOGIC;
        cin:IN STD_LOGIC;
        sum,cout:OUT STD_LOGIC
         );
END ENTITY f_adder;

ARCHITECTURE  arc1  OF  f_adder  IS
    SIGNAL  tmp:  STD_LOGIC;
BEGIN  
    tmp  <=  ain   XOR  bin  ;
     sum   <=  tmp  XOR  cin  ;
    cout   <=  (ain  AND  bin)  OR  (tmp  AND  cin)  ;
END  ARCHITECTURE  arc1;

LIBRARY  IEEE;
 USE  IEEE.STD_LOGIC_1164.ALL;
 USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 ENTITY test_fadder  IS 
 END ENTITY test_fadder;
  
 ARCHITECTURE arc1 OF test_fadder IS
     COMPONENT f_adder IS
         PORT(ain,bin:IN STD_LOGIC;
               cin:IN STD_LOGIC;
              cout,sum:OUT STD_LOGIC );
     END COMPONENT f_adder;

SIGNAL  test_a,test_b,test_c : STD_LOGIC;
SIGNAL  test_co,test_s:STD_LOGIC;

BEGIN
U0: f_adder PORT MAP (ain=>test_a ,bin=>test_b,cin=>test_c,
                     cout=>test_co,sum=>test_s); 

PROCESS
    BEGIN 
     test_a <= '0';
      WAIT FOR 400 ns;
     test_a <= '1';
      WAIT FOR 400 ns;
     test_a <= '0';
      WAIT FOR 200 ns;
     test_a <= '1';
      WAIT FOR 1000 ns;
     test_a <= '0';
      WAIT;
  END PROCESS;

PROCESS
    BEGIN 
     test_b <= '0';
      WAIT FOR 500 ns;
     test_b <= '1';
      WAIT FOR 800 ns;
     test_b <= '0';
      WAIT;
  END PROCESS;

PROCESS
    BEGIN 
     test_c <= '0';
      WAIT FOR 400 ns;
     test_c <= '1';
      WAIT FOR 700 ns;
     test_c <= '0';
      WAIT FOR 400 ns;
     test_c <= '1';
      WAIT FOR 600 ns;
     test_c <= '0';
      WAIT;
  END PROCESS;
END  ARCHITECTURE arc1;