// Copyright 2006, 2007 Dennis van Weeren//// This file is part of Minimig//// Minimig is free software; you can redistribute it and/or modify// it under the terms of the GNU General Public License as published by// the Free Software Foundation; either version 3 of the License, or// (at your option) any later version.//// Minimig is distributed in the hope that it will be useful,// but WITHOUT ANY WARRANTY; without even the implied warranty of// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the// GNU General Public License for more details.//// You should have received a copy of the GNU General Public License// along with this program.  If not, see <http://www.gnu.org/licenses/>.//////// This is the top module for the Minimig rev1.0 board//// 19-03-2005 		-started coding// 10-04-2005		-added cia's //				-verified timers a/b and I/O ports// 11-04-2005		-adapted top to cleaned up address decoder//				-connected cia's to .clk(~qclk) and .tick(e) for testing// 13-04-2005		-_foe and _loe are now made with clocks driving FF's//				-sram_bridge now also gets .clk(clk)// 18-04-2005		-added second synchronisation latch for mreset// 19-04-2005		-bootrom is now 2Kbyte large// 05-05-2005		-made preparations for dma (bus multiplexers between agnus and cpu)// 15-05-2005		-added denise// 				-connected vertb (vertical blank intterupt) to int3 input of paula// 18-05-2005		-removed interlaced top input pin// 28-06-2005		-done some experimentation to solve logic loop in Agnus// 17-07-2005		-connected second ram bank to hold kickstart rom// 				-added ovl (kickstart overlay) and boot (bootrom overlay) signals//				-wired cia in/out ports more correctly//				-wired vsync/hsync to cia's// 18-07-2005		-experimented to get kickstart running// 20-07-2005		-still experimenting..// 07-08-2005		-Jahoeee!! kickstart doesn't guru anymore but 'clicks' the floppy drive !//				-the guru's were caused by spurious writes to ram which is fixed now in the sram controller//				-unfortunately still no insert workbench screen but that may be caused by the missing blitter// 04-09-2005		-added blitter finished interrupt// 11-09-2005		-added 2meg addressing for Agnus// 13-09-2005		-added 4bit (per color) video output// 16-10-2005		-added user IO module// 23-10-2005		-added dmal signal wire// 08-11-2005		-fixed typo in instantiation of Paula// 21-11-2005		-added some signals to handle floppy// 22-11-2005		-adapted to new add-on develop board//				-added joystick 1 port// 10-12-2005		-done some experimentation to find floppy bug// 21-12-2005		-reworked code to use new style gary module// 27-12-2005		-added dskindx interrupt// 03-01-2006		-added dmas to avoid interference with copper cycles// 11-01-2006		-added Amber// 15-01-2006		-added syscontrol module to handle automatic boot sequence// 22-01-2006		-removed _csync port from agnus// 23-01-2006		-added fastblit input// 24-01-2006		-cia's now count positive _hsync/_vsync transitions// 14-02-2006		-code clean up//				-added fastchip input// 19-02-2006		-improved indx disk interrupt timing//				-cia timers now connect to sol/sof// 12-11-2006		-started porting code to Minimig rev1.0 board// 17-11-2006		-added address decoding for Minimig rev1.0 ram// 22-11-2006		-added keyboard reset// 27-11-2006		-code adapted to new synchronous bootrom// 03-12-2006		-added dimming powerled// 11-12-2006		-updated code to new ciaa// 27-12-2006		-updated code to new ciab// 24-06-2007		-moved cpu/sram/clock and syscontrol to this file to reduce number of source files//// TODO: 			-fixs bug and implement things I forgot.....//JB:// Important: if you are making any own fpga core builds please change fpga core id in BootRom.v
//
// 2008-07-17//	- scan doubler with vertical and horizontal interpolation//	- transparent osd window//	- selected osd line highlight//	- osd control by joystick (up and down pressed simultaneously invoke menu) //	- memory configuration from osd (512KB chip, 1MB chip, 512KB chip/512KB slow, 1MB chip/512KB slow)//	- video interpolation filter configuration from osd (vertical and horizontal)//	- user reset accessible from osd//	- user reset to bootloader (kickstart reloading)//	- new bootloader (text messages during kickstart loading)//	- ECS blitter//	- PAL/NTSC selection//	- modified display dma engine (better compatibility)//	- modified sprite dma engine (better compatibility)//	- modified copper timing (better compatibility) //	- modified floppy interface (better read and write support)//	- Action Replay III module for debugging (takes 512KB memory bank)
//
// Thanks to:
// Dennis for his great Minimig
// Loriano for impressive enclosure 
// Darrin and Oscar for their ideas, support and help
// Toni for his indispensable help and logic analyzer (and WinUAE :-)
//

module Minimig1(	//m68k pins	inout 	[15:0]cpudata,	//m68k data bus	input	[23:1]cpuaddress,	//m68k address bus	output	[2:0]_ipl,		//m68k interrupt request	input	_as,				//m68k address strobe	input	_uds,				//m68k upper data strobe	input	_lds,				//m68k lower data strobe	input	r_w,				//m68k read / write	output	_dtack,				//m68k data acknowledge	output	_cpureset,			//m68k reset	output	cpuclk,				//m68k clock	//sram pins	inout	[15:0]ramdata,	//sram data bus	output	[19:1]ramaddress,	//sram address bus	output	_ramsel0,			//sram enable bank 0	output	_ramsel1,			//sram enable bank 1	output	_ub,				//sram upper byte select	output	_lb,				//sram lower byte select	output	_we,				//sram write enable	output	_oe,				//sram output enable	//system	pins	input	mclk,				//master system clock (4.433619MHz)	//rs232 pins	input	rxd,				//rs232 receive	output	txd,				//rs232 send	input	cts,				//rs232 clear to send	output	rts,				//rs232 request to send	//I/O	input	[5:0]_joy1,		//joystick 1 [fire2,fire,up,down,left,right] (default mouse port)	input	[5:0]_joy2,		//joystick 2 [fire2,fire,up,down,left,right] (default joystick port)	input	_15khz,				//scandoubler disable	output	pwrled,				//power led	inout	msdat,				//PS2 mouse data	inout	msclk,				//PS2 mouse clk	inout	kbddat,				//PS2 keyboard data	inout	kbdclk,				//PS2 keyboard clk	//host controller interface (SPI)	input	_spisel0,			//SPI enable 0	input	_spisel1,			//SPI enable 1	input	_spisel2,			//SPI enable 2	input	spidin,				//SPI data input	output	spidout,			//SPI data output	input	spiclk,				//SPI clock	//video	output	_hsyncout,			//horizontal sync	output	_vsyncout,			//vertical sync	output	[3:0]redout,		//red	output	[3:0]greenout,	//green	output	[3:0]blueout,		//blue	//audio	output	left,				//audio bitstream left	output	right,				//audio bitstream right	//user i/o	output	gpio0,	output	gpio1,	output	gpio2);//--------------------------------------------------------------------------------------	parameter NTSC = 0;	//Agnus type (PAL/NTSC)//--------------------------------------------------------------------------------------//local signals for data buswire		[15:0]data;			//main databuswire		[15:0]pauladataout;	//paula databus outwire		[15:0]userdataout;	//user IO data outwire		[15:0]denisedataout;	//denise databus outwire		[15:0]cpudataout;		//cpu databus outwire		[15:0]ramdataout;		//ram databus outwire		[15:0]bootdataout;	//boot rom databus outwire		[15:0]ciadataout;		//cia A+B databus outwire		[15:0]agnusdataout;	//agnus data outwire		[15:0]cartdataout;	//Action Replay data out//local signals for spi buswire		paulaspidout; 		//paula spi data outwire		userspidout;		//userio spi data out//local signals for address busreg			[23:1]address;		//main address buswire		[20:1]address_agnus;//agnus address out//local signals for control buswire		hwr;			//main high write enable wire		lwr;			//main low write enable wire		rd;				//main read enablewire		cpurd; 			//cpu read enablewire		cpuhwr;			//cpu high write enablewire		cpulwr;			//cpu low write enablewire		dma;			//agnus gets buswire		dmawr;			//agnus writewire		dmapri;			//agnus has priority	//register address buswire		[8:1]regaddress; 	//main register address bus//rest of local signalswire		kbdrst;			//keyboard resetwire		reset;			//global resetwire		clk;			//bus clockwire		clk28m;			//28MHz clock for Amber (and ECS Denise in future)wire		qclk;			//qudrature bus clockwire		e;				//e clock enablewire		ovl;			//kickstart overlay enablewire		_led;			//power ledwire		boot;    		//bootrom overlay enablewire		selchip;		//chip ram selectwire		selslow;		//slow ram selectwire		selkick;		//rom selectwire		selreg;			//chip register selectwire		selciaa;		//cia A selectwire		selciab;		//cia B selectwire		selboot;		//boot rom selectwire		int2;			//intterrupt 2wire		int3;			//intterrupt 3 wire		int6;			//intterrupt 6wire		[5:0]osdctrl;	//OSD control (minimig->host, [menu,select,down,up])wire		_fire0;			//joystick 1 fire signal	to cia Awire		_fire1;			//joystick 2 fire signal to cia Awire		[2:0]user;	//user control signalswire		dmal;			//dma request from Paula to Agnuswire		dmas;			//dma special from Paula to Agnuswire		indx;			//disk index interrupt//local video signalswire		blank;			//blanking signalwire		sol;			//start of video linewire		sof;			//start of video framewire		strhor;			//horizontal strobe for Denisewire		[3:0]nred;	//denise (pal) redwire		[3:0]ngreen;	//denise (pal) greenwire		[3:0]nblue;	//denise (pal) bluewire		osdblank;		//osd blanking wire		osdpixel;		//osd pixel(video) datawire		_hsync;			//horizontal syncwire		_vsync;			//vertical sync//local floppy signals (CIA<-->Paula)wire		_step;			//step heads of diskwire		direc;			//step heads directionwire		_sel0;			//disk0 select 	wire		_sel1;			//disk1 select 	wire		_sel2;			//disk2 select 	wire		_sel3;			//disk3 select 	wire		side;			//upper/lower disk headwire		_motor;			//disk motor controlwire		_track0;		//track zero detectwire		_change;		//disk has been removed from drivewire		_ready;			//disk is readywire		_wprot;			//disk is write-protected//--------------------------------------------------------------------------------------//JB:wire	int7;				//int7 interrupt request from Action Replaywire	[2:0]_iplx;		//interrupt request lines from paulawire	selcart;			//Action Replay RAM selectwire	ovr;				//overide chip memmory decodingwire	usrrst;				//user reset from osd interfacewire	bootrst;			//user reset to bootloaderwire	[1:0]lr_filter;	//bit #0: horizontal, bit #1: verticalwire	[1:0]hr_filter;wire	hires;				//hires signal from denisewire	[1:0]memcfg;		//memory configuration (0: only 512KB chip, 1: 1MB chip, 2: 512KB chip / 512KB slow, 3: 1MB chip / 512KB slow)reg		extra_chip;			//extra chip ram is activatedreg		extra_slow;			//extra slow ram is activatedwire	aron;				//Action Replay is enabled//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//power led control//when _led=0, pwrled=on//when _led=1, pwrled=powered by weak pullupassign pwrled=(_led)?1'bz:1'b1;assign {gpio2,gpio1,gpio0} = 3'b000;//--------------------------------------------------------------------------------------//indx signal generation, this signal is the disk index interrupt and is needed to let some//loaders function correctly//indx is asserted every 10 scanlines to simulate disk at 300 RPMreg [3:0]indxcnt;always @(posedge clk)	if(indx)		indxcnt[3:0]<=0;	else if(sof)		indxcnt[3:0]<=indxcnt[3:0]+1;		assign indx=(indxcnt[3:0]==9)?1:0;//--------------------------------------------------------------------------------------//switch address and control bus between agnus and cpualways @(dma or cpuaddress or address_agnus)	if(!dma)//address bus and control bus belongs to cpu		address[23:1]=cpuaddress[23:1];	else//address bus and control bus belongs to agnus		address[23:1]={cpuaddress[23:21],address_agnus[20:1]};//--------------------------------------------------------------------------------------//instantiate agnusAgnus A1(	.clk(clk),	.clk28m(clk28m),	.reset(reset),	.aen(selreg),	.rd(rd),	.hwr(hwr),	.lwr(lwr),	.datain(data),	.dataout(agnusdataout),	.addressin(address[8:1]),	.addressout(address_agnus),	.regaddress(regaddress),	.bus(dma),	.buswr(dmawr),	.buspri(dmapri),	._hsync(_hsync),	._vsync(_vsync),	.blank(blank),	.sol(sol),	.sof(sof),	.strhor(strhor),	.int3(int3),	.dmal(dmal),	.dmas(dmas),	.ntsc(NTSC),	.fastchip(1'b0));//instantiate paulaPaula P1(	.clk(clk),	.reset(reset),	.regaddress(regaddress),	.datain(data),	.dataout(pauladataout),	.txd(txd),	.rxd(rxd),	.sol(sol),	.sof(sof),	.int2(int2),	.int3(int3),	.int6(int6),	._ipl(_iplx),	.dmal(dmal),	.dmas(dmas),	._step(_step),	.direc(direc),	._sel(_sel0),	.side(side),	._motor(_motor),	._track0(_track0),	._change(_change),	._ready(_ready),	._wprot(_wprot), //JB: disk is write-protected	._den(_spisel0),	.din(spidin),	.dout(paulaspidout),	.dclk(spiclk),	.user(user),	.left(left),	.right(right));//instantiate user IOuserio UI1 (		.clk(clk),	.reset(reset),	.sol(sol),	.sof(sof),	.regaddress(regaddress),	.datain(data),	.dataout(userdataout),	.ps2mdat(msdat),	.ps2mclk(msclk),	._fire0(_fire0),	._fire1(_fire1),	.user(user),	._joy1(_joy1),	._joy2(_joy2),	.osdctrl(osdctrl[3:0]),	._den(_spisel1),	.din(spidin),	.dout(userspidout),	.dclk(spiclk),	.osdblank(osdblank),	.osdpixel(osdpixel),	.lr_filter(lr_filter),	.hr_filter(hr_filter),	.memcfg(memcfg),	.usrrst(usrrst),	.bootrst(bootrst));//memory configuration changed during resetalways @(posedge clk)	if (reset)		{extra_slow,extra_chip} <= memcfg;//instantiate DeniseDenise DN1(			.clk(clk),	.reset(reset),	.sol(sol),	.sof(sof),	.strhor(strhor),	.regaddress(regaddress),	.datain(data),	.dataout(denisedataout),	.blank(blank),	.red(nred),	.green(ngreen),	.blue(nblue),	.hires(hires));//instantiate AmberAmber AMB1(			.clk(clk),	.clk28m(clk28m),	.dblscan(_15khz),	.lr_filter(lr_filter),	.hr_filter(hr_filter),	.hires(hires),	.osdblank(osdblank),	.osdpixel(osdpixel),	.redin(nred),	.bluein(nblue),	.greenin(ngreen),	._hsyncin(_hsync),	._vsyncin(_vsync),	.redout(redout),	.blueout(blueout),	.greenout(greenout),	._hsyncout(_hsyncout),	._vsyncout(_vsyncout));//instantiate cia Aciaa ciaa(