// Copyright 2006, 2007 Dennis van Weeren//// This file is part of Minimig//// Minimig is free software; you can redistribute it and/or modify// it under the terms of the GNU General Public License as published by// the Free Software Foundation; either version 3 of the License, or// (at your option) any later version.//// Minimig is distributed in the hope that it will be useful,// but WITHOUT ANY WARRANTY; without even the implied warranty of// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the// GNU General Public License for more details.//// You should have received a copy of the GNU General Public License// along with this program.  If not, see <http://www.gnu.org/licenses/>.//////// This is paula//// 06-03-2005		-started coding// 19-03-2005		-added interupt controller and uart// 04-09-2005		-added blitter finished interrupt// 19-10-2005		-removed cck (color clock enable) input//				-removed intb signal//				-added sof signal// 23-10-2005		-added dmal signal//				-added paula part of DMACON// 21-11-2005		-added floppy controller// 				-added ADKCON/ADCONR registers//				-added local horbeam counter// 27-11-2005		-den is now active low (_den)//				-some typo's fixed// 11-12-2005		-disable syncword interrupt// 13-12-2005		-enable syncword interrupt// 27-12-2005		-cleaned up code// 28-12-2005		-added audio module// 03-01-2006		-added dmas to avoid interference with copper cycles// 07-01-2006		-added dmas for disk controller// 06-02-2006		-added user disk control input// 03-07-2007		-moved interrupt controller and uart to this file to reduce number of sourcefilesmodule Paula(
	//bus interface 	input 	clk,		    	//bus clock	input 	reset,			   	//reset 	input 	[8:1]regaddress,	//register address inputs	input	[15:0]datain,		//bus data in	output	[15:0]dataout,	//bus data out	//serial (uart) 	output 	txd,				//serial port transmitted data	input 	rxd,		  		//serial port received data	//interrupts and dma	input	sol,				//start of video line	input	sof,				//start of video frame (triggers vertical blank interrupt)	input	int2,				//level 2 interrupt	input	int3,				//level 3 interrupt	input	int6,				//level 6 interrupt	output	[2:0]_ipl,		//m68k interrupt request	output	dmal,				//dma request (to Agnus)	output	dmas,				//dma special (to Agnus)	//disk control signals from cia and user	input	[2:0]user,		//user disk control	input	_step,				//step heads of disk	input	direc,				//step heads direction	input	_sel,				//disk select 		input	side,				//upper/lower disk head	input	_motor,				//disk motor control	output	_track0,			//track zero detect	output	_change,			//disk has been removed from drive	output	_ready,				//disk is ready	output	_wprot,				//disk is write-protected	//flash drive host controller interface	(SPI)	input	_den,				//async. serial data enable	input	din,				//async. serial data input	output	dout,				//async. serial data output	input	dclk,				//async. serial data clock	//audio outputs	output	left,				//audio bitstream left	output	right				//audio bitstream right);//--------------------------------------------------------------------------------------//register names and addressesparameter DMACON=9'h096;	parameter ADKCON=9'h09e;parameter ADKCONR=9'h010;	//local signalsreg		[4:0]dmacon;			//dmacon paula bits reg		dmaen;					//master dma enablereg		[14:0]adkcon;			//audio and disk control registerreg		[8:0]horbeam;			//horizontal beamcounterwire	[15:0]uartdataout; 	//UART data outwire	[15:0]intdataout;  	//interrupt controller data outwire	[15:0]diskdataout;	//disk controller data outwire	[15:0]adkconr;		//ADKCONR register data outwire	diskdmal;				//disk dma requestwire	audiodmal;				//audio dma requestwire	diskdmas;				//disk dma sepcialwire	audiodmas;				//audio dma specialwire	rbfmirror; 				//rbf mirror (from uart to interrupt controller)wire	rxint;  				//uart rx interrupt requestwire	txint;					//uart tx interrupt requestwire	blckint;				//disk block finished interruptwire	syncint;				//disk syncword match interruptwire	[3:0]audint;			//audio channels 0,1,2,3 interrupt requestwire	[3:0]audpen;			//audio channels 0,1,2,3 interrupt pendingwire	[3:0]auden;			//audio channels 0,1,2,3 dma enablewire	dsken; 					//disk dma enable//--------------------------------------------------------------------------------------//dataout multiplexerassign dataout=uartdataout|intdataout|diskdataout|adkconr;//dma request multiplexerassign dmal=diskdmal|audiodmal;//dma special multiplexerassign dmas=diskdmas|audiodmas;//--------------------------------------------------------------------------------------//DMACON register write//NOTE: this register is also present in the Agnus module,//there DMACONR (read) is implementedalways @(posedge clk)	if(reset)		dmacon<=0;	else if(regaddress[8:1]==DMACON[8:1])	begin		if(datain[15])			{dmaen,dmacon[4:0]}<={dmaen,dmacon[4:0]}|{datain[9],datain[4:0]};		else			{dmaen,dmacon[4:0]}<={dmaen,dmacon[4:0]}&(~{datain[9],datain[4:0]});		end//assign disk and audio dma enable bitsassign	dsken=dmacon[4]&dmaen;assign	auden[3]=dmacon[3]&dmaen;assign	auden[2]=dmacon[2]&dmaen;assign	auden[1]=dmacon[1]&dmaen;assign	auden[0]=dmacon[0]&dmaen;//--------------------------------------------------------------------------------------//ADKCON register writealways @(posedge clk)	if(reset)		adkcon<=0;	else if(regaddress[8:1]==ADKCON[8:1])	begin		if(datain[15])			adkcon[14:0]<=adkcon[14:0]|datain[14:0];		else			adkcon[14:0]<=adkcon[14:0]&(~datain[14:0]);		end//ADKCONR register assign adkconr[15:0]=(regaddress[8:1]==ADKCONR[8:1])?{1'b0,adkcon[14:0]}:16'h0000;//--------------------------------------------------------------------------------------//Paula local beamcounteralways @(posedge clk)	if(sol)		horbeam<=0;	else		horbeam<=horbeam+1;//--------------------------------------------------------------------------------------//instantiate uartuart pu1(	.clk(clk),	.reset(reset),	.regaddress(regaddress),	.datain(datain[14:0]),	.dataout(uartdataout),	.rbfmirror(rbfmirror),	.rxint(rxint),	.txint(txint),	.rxd(rxd),	.txd(txd));//instantiate interrupt controllerintcontroller pi1(	.clk(clk),	.reset(reset),	.regaddress(regaddress),	.datain(datain),	.dataout(intdataout),	.rxint(rxint),	.txint(txint),	.sof(sof),	.int2(int2),	.int3(int3),	.int6(int6),	.blckint(blckint),	.syncint(syncint),	.audint(audint),	.audpen(audpen),	.rbfmirror(rbfmirror),	._ipl(_ipl));//instantiate floppy controller / flashdrive host interfacefloppy pf1(
	.clk(clk),	.reset(reset),	.enable(dsken),	.horbeam(horbeam),	.regaddress(regaddress),	.datain(datain),	.dataout(diskdataout),	.dmal(diskdmal),	.dmas(diskdmas),	.user(user),	._step(_step),	.direc(direc),	._sel(_sel),	.side(side),	._motor(_motor),	._track0(_track0),	._change(_change),	._ready(_ready),	._wprot(_wprot),	.blckint(blckint),	.syncint(syncint),	.wordsync(adkcon[10]),	._den(_den),	.din(din),	.dout(dout),	.dclk(dclk));//instantiate audio controlleraudio ad1(		.clk(clk),	.reset(reset),	.horbeam(horbeam),	.regaddress(regaddress),	.datain(datain),	.dmacon(auden[3:0]),	.audint(audint[3:0]),	.audpen(audpen),	.dmal(audiodmal),	.dmas(audiodmas),	.left(left),	.right(right)	);//--------------------------------------------------------------------------------------endmodule//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------/*interrupt controller*/module intcontroller(	input 	clk,		    	//bus clock	input 	reset,			   	//reset 	input 	[8:1] regaddress,	//register address inputs	input	[15:0]datain,		//bus data in	output	[15:0]dataout,	//bus data out	input	rxint,				//uart receive interrupt	input	txint,				//uart transmit interrupt	input	sof,				//start of video frame	input	int2,				//level 2 interrupt	input	int3,				//level 3 interrupt	input	int6,				//level 6 interrupt	input	blckint,			//disk block finished interrupt	input	syncint,			//disk syncword match interrupt	input	[3:0]audint,		//audio channels 0,1,2,3 interrupts	output	[3:0]audpen,		//mirror of audio interrupts for audio controller	output	rbfmirror,			//mirror of serial receive interrupt for uart SERDATR register	output	reg [2:0]_ipl		//m68k interrupt request);//register names and addresses		parameter INTENAR=9'h01c;parameter INTREQR=9'h01e;parameter INTENA=9'h09a;parameter INTREQ=9'h09c;//local signalsreg		[14:0]intena;			//int enable write registerreg 	[15:0]intenar;			//int enable read registerreg		[13:0]intreq;			//int request registerreg		[15:0]intreqr;			//int request readback//rbf mirror outassign rbfmirror=intreq[11];//audio mirror outassign audpen[3:0]=intreq[10:7];//dataout	multiplexerassign dataout=intenar|intreqr;//intena registeralways @(posedge clk)	if(reset)		intena<=0;	else if(regaddress[8:1]==INTENA[8:1])	begin		if(datain[15])