begin	if(!window)//we are outside the visible window region, display border color		tabledata=6'b000000;	else if(homod || sprsel_d)//if HAM mode or sprsel, select sprites		tabledata={2'b01,sprdata_d[3:0]};	else//else select playfield data		tabledata=plfdata_d;end//hamrgb / tablergb multiplexeralways @(homod or sprsel_d or window or tablergb or hamrgb)begin	if(!homod)//if no HAM mode, always select normal (table selected) rgb data		outrgb=tablergb;	else if (!window || sprsel_d)//else if outside window or sprite priority		outrgb=tablergb;	else//else select ham generated rgb value		outrgb=hamrgb;end//--------------------------------------------------------------------------------------//video output register (ddr) and blanking circuitreg [11:0]outrgbl1;reg [11:0]outrgbl2;always @(negedge clk)	if(blank)		outrgbl1<=12'b000000000000;	else		outrgbl1<=outrgb;always @(posedge clk)	if(blank)		outrgbl2<=12'b000000000000;	else		outrgbl2<=outrgb;//output ddr mulitplexerassign {red[3:0],green[3:0],blue[3:0]}=(dclk)?outrgbl1:outrgbl2;endmodule//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//this is the 32color color table//because this module also supports EHB (extra half brite) mode,//it actually has a 6bit color select input//the 6th bit selects EHB color while the lower 5 bit select the actual color registermodule colortable(clk,regaddress,datain,select,rgb);input 	clk;		   			//bus clock / lores pixel clockinput 	[8:1] regaddress;		//register adress inputsinput 	[11:0] datain;			//bus data ininput	[5:0] select;			//color select inputoutput	[11:0] rgb;			//RGB output//register names and adresses		parameter COLORBASE=9'h180;  		//color table base address//local signalsreg 		[11:0]colortable[31:0];	//color tablewire		[11:0]selcolor; 		//selected color register outputreg		[11:0]rgb;			//see above//writing of color table from bus (implemented using dual port distributed ram)always @(posedge clk)	if (regaddress[8:6]==COLORBASE[8:6])		colortable[regaddress[5:1]]<=datain[11:0];//reading of color tableassign selcolor=colortable[select[4:0]];   //extra half brite mode shifteralways @(selcolor or select[5])	if(select[5])//half bright, shift every component 1 position to the right		rgb={1'b0,selcolor[11:9],1'b0,selcolor[7:5],1'b0,selcolor[3:1]};	else//normal color select		rgb=selcolor;endmodule//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//sprite priority logic module//this module checks the playfields and sprites video status and//determines if playfield or sprite data must be sent to the video output//sprite/playfield priority is configurable through the bplcon2 bits				module sprpriority(bplcon2,nplayfield,nsprite,sprsel);input 	[5:0]bplcon2;		   	//playfields vs sprites priority settinginput	[2:1]nplayfield;		//playfields video statusinput	[7:0]nsprite;			//sprites video statusoutput	sprsel;				//sprites select signal output// local signalsreg		sprsel;				//see abovereg		[2:0]sprcode;			//sprite codewire		[3:0]sprgroup;			//grouped spriteswire		pf1front;				//playfield 1 is on front of spriteswire		pf2front;				//playfield 2 is on front of sprites//group sprites togetherassign	sprgroup[0]=(nsprite[1:0]==0)?0:1;assign	sprgroup[1]=(nsprite[3:2]==0)?0:1;assign	sprgroup[2]=(nsprite[5:4]==0)?0:1;assign	sprgroup[3]=(nsprite[7:6]==0)?0:1;//sprites priority encoderalways @(sprgroup)	if(sprgroup[0])		sprcode=1;	else if(sprgroup[1])		sprcode=2;	else if(sprgroup[2])		sprcode=3;	else if(sprgroup[3])		sprcode=4;	else		sprcode=7;//check if playfields are in front of spritesassign pf1front=(sprcode[2:0]>bplcon2[2:0])?1:0;assign pf2front=(sprcode[2:0]>bplcon2[5:3])?1:0;//generate final playfield/sprite select signalalways @(sprcode or pf1front or pf2front or nplayfield)begin	if(sprcode[2:0]==7)//if no valid sprite data, always select playfields		sprsel=0;	else if(pf1front && nplayfield[1])//else if pf1 in front and valid data, select playfields		sprsel=0;	else if(pf2front && nplayfield[2])//else if pf2 in front and valid data, select playfields		sprsel=0;	 	else//else select sprites		sprsel=1;endendmodule//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//this module handles the hold and modify mode (HAM)//the module has its own color pallete bank, this is to let //the sprites run simultanously with a HAM playfieldmodule hamgenerator(clk,regaddress,datain,bpldata,rgb);input 	clk;		   			//bus clock / lores pixel clockinput 	[8:1]regaddress;		//register adress inputsinput 	[11:0]datain;			//bus data ininput	[5:0]bpldata;			//bitplane data inputoutput	[11:0]rgb;			//RGB output//register names and adresses		parameter COLORBASE=9'h180;  		//color table base address//local signalsreg		[11:0]rgb;			//rgb output registerreg 		[11:0]colortable[15:0];	//color tablewire		[11:0]selcolor;		//selected color output from color table//--------------------------------------------------------------------------------------//writing of HAM color table from bus (implemented using dual port distributed ram)always @(posedge clk)	if (regaddress[8:5]==COLORBASE[8:5])		colortable[regaddress[4:1]]<=datain[11:0];//reading of color tableassign selcolor=colortable[bpldata[3:0]];   //--------------------------------------------------------------------------------------//HAM instruction decoder/processoralways @(posedge clk)begin	case(bpldata[5:4])		2'b00://load rgb output with color from table				rgb<=selcolor;		2'b01://hold green and red, modify blue			rgb<={rgb[11:4],bpldata[3:0]};			2'b10://hold green and blue, modify red			rgb<={bpldata[3:0],rgb[7:0]};		2'b11://hold blue and red, modify green			rgb<={rgb[11:8],bpldata[3:0],rgb[3:0]};	endcaseendendmodule//--------------------------------------------------------------------------------------//--------------------------------------------------------------------------------------//this is the collision detection modulemodule collision(clk,reset,regaddress,datain,dataout,bpldata,nsprite);input 	clk;		   			//bus clock / lores pixel clockinput	reset;				//resetinput 	[8:1]regaddress;		//register adress inputsinput 	[15:0]datain;			//bus data inoutput	[15:0]dataout;			//bus data outinput	[5:0]bpldata;			//bitplane serial video data ininput	[7:0]nsprite;			//sprites video status in//register names and adresses		parameter CLXCON=9'h098;parameter CLXDAT=9'h00e;//local signalsreg		[15:0]clxcon;			//collision detection control registerreg		[14:0]clxdat;			//collision detection data registerwire		[3:0]sprmatch;			//sprite group matches clxcon settingswire		oddmatch;				//odd bitplane data matches clxcon settingswire		evenmatch;			//even bitplane data matches clxcon settings//--------------------------------------------------------------------------------------//CLXCON registeralways @(posedge clk)	if(reset)//reset to safe value		clxcon<=16'h0fff;	else if(regaddress[8:1]==CLXCON[8:1])		clxcon<=datain;//--------------------------------------------------------------------------------------//generate bitplane match signalwire [5:0]bm;assign bm=(bpldata[5:0]^clxcon[5:0])|(~clxcon[11:6]);assign oddmatch=bm[4]&bm[2]&bm[0];assign evenmatch=bm[5]&bm[3]&bm[1];//generate sprite group match signalassign sprmatch[0]=nsprite[0]|(nsprite[1]&clxcon[12]);assign sprmatch[1]=nsprite[2]|(nsprite[3]&clxcon[13]);assign sprmatch[2]=nsprite[4]|(nsprite[5]&clxcon[14]);assign sprmatch[3]=nsprite[6]|(nsprite[7]&clxcon[15]);//--------------------------------------------------------------------------------------//detect collisionswire [14:0]cl;assign cl[0]=evenmatch&oddmatch;//odd to even bitplanesassign cl[1]=oddmatch&sprmatch[0];//odd bitplanes to sprite 0(or 1)assign cl[2]=oddmatch&sprmatch[1];//odd bitplanes to sprite 2(or 3)assign cl[3]=oddmatch&sprmatch[2];//odd bitplanes to sprite 4(or 5)assign cl[4]=oddmatch&sprmatch[3];//odd bitplanes to sprite 6(or 7)assign cl[5]=evenmatch&sprmatch[0];//even bitplanes to sprite 0(or 1)assign cl[6]=evenmatch&sprmatch[1];//even bitplanes to sprite 2(or 3)assign cl[7]=evenmatch&sprmatch[2];//even bitplanes to sprite 4(or 5)assign cl[8]=evenmatch&sprmatch[3];//even bitplanes to sprite 6(or 7)assign cl[9]=sprmatch[0]&sprmatch[1];//sprite 0(or 1) to sprite 2(or 3)assign cl[10]=sprmatch[0]&sprmatch[2];//sprite 0(or 1) to sprite 4(or 5)assign cl[11]=sprmatch[0]&sprmatch[3];//sprite 0(or 1) to sprite 6(or 7)assign cl[12]=sprmatch[1]&sprmatch[2];//sprite 2(or 3) to sprite 4(or 5)assign cl[13]=sprmatch[1]&sprmatch[3];//sprite 2(or 3) to sprite 6(or 7)assign cl[14]=sprmatch[2]&sprmatch[3];//sprite 4(or 5) to sprite 6(or 7)//register detected collisionsalways @(posedge clk)	if(regaddress[8:1]==CLXDAT[8:1])//if clxdat is read, clxdat is cleared to all zero's		clxdat<=0;	else//else register collisions		clxdat<=clxdat[14:0]|cl[14:0];//--------------------------------------------------------------------------------------//reading of clxdat registerassign dataout=(regaddress[8:1]==CLXDAT[8:1])?{1'b1,clxdat[14:0]}:0;endmodule