library ieee;
use ieee.std_logic_1164.all;

entity cnt2 is
   port (clk:in std_logic;
         q:buffer integer range 0 to 3);
end cnt2;
 
architecture state of cnt2 is
  begin
  process(clk)
    begin
       if((clk'event)and(clk='1'))then
           if (q=3) then q<=0;
           else q<=q+1;
           end if;
       end if;
     end process; 
end state;