?? led7.rpt
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Project Information d:\mul4\led7.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/28/2006 18:45:43
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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net list, support information, device programming or simulation file, or
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their respective licensors. No other licenses, including any licenses
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***** Project compilation was successful
LED7
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
led7 EPM7032SLC44-5 9 7 0 26 6 81 %
User Pins: 9 7 0
Device-Specific Information: d:\mul4\led7.rpt
led7
***** Logic for device 'led7' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R R
E E
S S
E E
R R
V G G G G G V V
a e a C N N N N N E E
7 n 0 C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
a6 | 8 38 | #TDO
a5 | 9 37 | RESERVED
GND | 10 36 | RESERVED
a1 | 11 35 | VCC
a2 | 12 EPM7032SLC44-5 34 | RESERVED
#TMS | 13 33 | RESERVED
a3 | 14 32 | #TCK
VCC | 15 31 | RESERVED
a4 | 16 30 | GND
led0 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
l l l R G V R l l R l
e e e E N C E e e E e
d d d S D C S d d S d
1 4 5 E E 6 3 E 2
R R R
V V V
E E E
D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\mul4\led7.rpt
led7
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 15/16( 93%) 5/16( 31%) 17/36( 47%)
B: LC17 - LC32 16/16(100%) 5/16( 31%) 11/16( 68%) 21/36( 58%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 20/32 ( 62%)
Total logic cells used: 26/32 ( 81%)
Total shareable expanders used: 6/32 ( 18%)
Total Turbo logic cells used: 26/32 ( 81%)
Total shareable expanders not available (n/a): 10/32 ( 31%)
Average fan-in: 6.88
Total fan-in: 179
Total input pins required: 9
Total fast input logic cells required: 0
Total output pins required: 7
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 26
Total flipflops required: 0
Total product terms required: 100
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 19/ 32 ( 59%)
Device-Specific Information: d:\mul4\led7.rpt
led7
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 0 15 a0
11 (7) (A) INPUT 0 0 0 0 0 0 15 a1
12 (8) (A) INPUT 0 0 0 0 0 0 15 a2
14 (10) (A) INPUT 0 0 0 0 0 0 15 a3
16 (11) (A) INPUT 0 0 0 0 0 0 15 a4
9 (6) (A) INPUT 0 0 0 0 0 0 15 a5
8 (5) (A) INPUT 0 0 0 0 0 0 15 a6
6 (3) (A) INPUT 0 0 0 0 0 0 15 a7
5 (2) (A) INPUT 0 0 0 0 0 7 11 en
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\mul4\led7.rpt
led7
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 12 A OUTPUT t 0 0 0 1 2 0 0 led0
18 13 A OUTPUT t 0 0 0 1 2 0 0 led1
28 28 B OUTPUT t 0 0 0 1 2 0 0 led2
26 30 B OUTPUT t 0 0 0 1 2 0 0 led3
19 14 A OUTPUT t 0 0 0 1 2 0 0 led4
20 15 A OUTPUT t 0 0 0 1 2 0 0 led5
25 31 B OUTPUT t 0 0 0 1 2 0 0 led6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\mul4\led7.rpt
led7
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT s t 1 1 0 8 1 1 0 ~708~1
(21) 16 A SOFT s t 3 1 1 8 1 1 1 ~759~1
(5) 2 A SOFT s t 2 1 1 8 1 1 1 ~810~1
(31) 26 B SOFT s t 2 2 0 8 1 1 0 ~861~1
(33) 24 B SOFT s t 2 1 1 8 1 1 0 ~912~1
(27) 29 B SOFT s t 1 1 0 8 1 1 0 ~963~1
(4) 1 A SOFT s t 2 2 0 8 1 1 1 ~1014~1
(40) 18 B LCELL s t 2 1 1 9 1 0 1 ~1033~1~2
(39) 19 B LCELL s t 2 1 1 9 2 1 3 ~1033~1
(9) 6 A LCELL s t 0 0 0 1 2 1 2 ~1039~1
(8) 5 A LCELL s t 0 0 0 1 2 1 2 ~1045~1
(36) 22 B LCELL s t 3 2 1 9 1 0 1 ~1051~1~2
(37) 21 B LCELL s t 0 0 0 1 2 0 1 ~1051~1~3
(38) 20 B LCELL s t 3 2 1 9 2 1 4 ~1051~1
(34) 23 B LCELL s t 2 2 0 8 1 0 1 ~1057~1~2
(32) 25 B LCELL s t 3 2 1 9 2 1 3 ~1057~1
(29) 27 B LCELL s t 2 1 1 9 1 0 1 ~1063~1~2
(41) 17 B LCELL s t 2 1 1 9 2 1 3 ~1063~1
(12) 8 A LCELL s t 0 0 0 1 2 1 2 ~1069~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\mul4\led7.rpt
led7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC12 led0
| +----------------- LC13 led1
| | +--------------- LC14 led4
| | | +------------- LC15 led5
| | | | +----------- LC16 ~759~1
| | | | | +--------- LC2 ~810~1
| | | | | | +------- LC1 ~1014~1
| | | | | | | +----- LC6 ~1039~1
| | | | | | | | +--- LC5 ~1045~1
| | | | | | | | | +- LC8 ~1069~1
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC16 -> - - - * - - - * - - | * - | <-- ~759~1
LC2 -> - - * - - - - - * - | * - | <-- ~810~1
LC1 -> * - - - - - - - - * | * - | <-- ~1014~1
LC6 -> - - - * * - - * - - | * - | <-- ~1039~1
LC5 -> - - * - - * - - * - | * - | <-- ~1045~1
LC8 -> * - - - - - * - - * | * - | <-- ~1069~1
Pin
4 -> - - - - * * * - - - | * * | <-- a0
11 -> - - - - * * * - - - | * * | <-- a1
12 -> - - - - * * * - - - | * * | <-- a2
14 -> - - - - * * * - - - | * * | <-- a3
16 -> - - - - * * * - - - | * * | <-- a4
9 -> - - - - * * * - - - | * * | <-- a5
8 -> - - - - * * * - - - | * * | <-- a6
6 -> - - - - * * * - - - | * * | <-- a7
5 -> * * * * - - - * * * | * * | <-- en
LC29 -> - * - - - - - - - - | * - | <-- ~963~1
LC17 -> - * - - - - - - - - | * * | <-- ~1063~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mul4\led7.rpt
led7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC28 led2
| +----------------------------- LC30 led3
| | +--------------------------- LC31 led6
| | | +------------------------- LC32 ~708~1
| | | | +----------------------- LC26 ~861~1
| | | | | +--------------------- LC24 ~912~1
| | | | | | +------------------- LC29 ~963~1
| | | | | | | +----------------- LC18 ~1033~1~2
| | | | | | | | +--------------- LC19 ~1033~1
| | | | | | | | | +------------- LC22 ~1051~1~2
| | | | | | | | | | +----------- LC21 ~1051~1~3
| | | | | | | | | | | +--------- LC20 ~1051~1
| | | | | | | | | | | | +------- LC23 ~1057~1~2
| | | | | | | | | | | | | +----- LC25 ~1057~1
| | | | | | | | | | | | | | +--- LC27 ~1063~1~2
| | | | | | | | | | | | | | | +- LC17 ~1063~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC32 -> - - * - - - - - - - - - - - - - | - * | <-- ~708~1
LC26 -> - * - - - - - - - - - - - - - - | - * | <-- ~861~1
LC24 -> * - - - - - - - - - - - - - - - | - * | <-- ~912~1
LC18 -> - - - - - - - - * - - - - - - - | - * | <-- ~1033~1~2
LC19 -> - - * * - - - * * - - - - - - - | - * | <-- ~1033~1
LC22 -> - - - - - - - - - - * - - - - - | - * | <-- ~1051~1~2
LC21 -> - - - - - - - - - - - * - - - - | - * | <-- ~1051~1~3
LC20 -> - * - - * - - - - * * * - - - - | - * | <-- ~1051~1
LC23 -> - - - - - - - - - - - - - * - - | - * | <-- ~1057~1~2
LC25 -> * - - - - * - - - - - - * * - - | - * | <-- ~1057~1
LC27 -> - - - - - - - - - - - - - - - * | - * | <-- ~1063~1~2
LC17 -> - - - - - - * - - - - - - - * * | * * | <-- ~1063~1
Pin
4 -> - - - * * * * * * * - * * * * * | * * | <-- a0
11 -> - - - * * * * * * * - * * * * * | * * | <-- a1
12 -> - - - * * * * * * * - * * * * * | * * | <-- a2
14 -> - - - * * * * * * * - * * * * * | * * | <-- a3
16 -> - - - * * * * * * * - * * * * * | * * | <-- a4
9 -> - - - * * * * * * * - * * * * * | * * | <-- a5
8 -> - - - * * * * * * * - * * * * * | * * | <-- a6
6 -> - - - * * * * * * * - * * * * * | * * | <-- a7
5 -> * * * - - - - * * * * * - * * * | * * | <-- en
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mul4\led7.rpt
led7
** EQUATIONS **
a0 : INPUT;
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