a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
a4       : INPUT;
a5       : INPUT;
a6       : INPUT;
a7       : INPUT;
en       : INPUT;

-- Node name is 'led0' 
-- Equation name is 'led0', location is LC012, type is output.
 led0    = LCELL( _EQ001 $  GND);
  _EQ001 =  en &  _LC001
         # !en &  _LC008;

-- Node name is 'led1' 
-- Equation name is 'led1', location is LC013, type is output.
 led1    = LCELL( _EQ002 $  GND);
  _EQ002 =  en &  _LC029
         # !en &  _LC017;

-- Node name is 'led2' 
-- Equation name is 'led2', location is LC028, type is output.
 led2    = LCELL( _EQ003 $  GND);
  _EQ003 =  en &  _LC024
         # !en &  _LC025;

-- Node name is 'led3' 
-- Equation name is 'led3', location is LC030, type is output.
 led3    = LCELL( _EQ004 $  GND);
  _EQ004 =  en &  _LC026
         # !en &  _LC020;

-- Node name is 'led4' 
-- Equation name is 'led4', location is LC014, type is output.
 led4    = LCELL( _EQ005 $  GND);
  _EQ005 =  en &  _LC002
         # !en &  _LC005;

-- Node name is 'led5' 
-- Equation name is 'led5', location is LC015, type is output.
 led5    = LCELL( _EQ006 $  GND);
  _EQ006 =  en &  _LC016
         # !en &  _LC006;

-- Node name is 'led6' 
-- Equation name is 'led6', location is LC031, type is output.
 led6    = LCELL( _EQ007 $  GND);
  _EQ007 =  en &  _LC032
         # !en &  _LC019;

-- Node name is '~708~1' 
-- Equation name is '~708~1', location is LC032, type is buried.
-- synthesized logic cell 
_LC032   = LCELL( _EQ008 $  VCC);
  _EQ008 =  a0 &  a1 &  a2 & !a3 & !a4 & !a5 & !a6 & !a7
         # !a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a0 & !a1 & !a2 & !a3 & !a4 & !a5 & !a6 & !a7
         # !_LC019 &  _X001;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~759~1' 
-- Equation name is '~759~1', location is LC016, type is buried.
-- synthesized logic cell 
_LC016   = LCELL( _EQ009 $  VCC);
  _EQ009 =  a0 & !a1 &  a2 & !a3 & !a4 & !a5 & !a6 & !a7
         # !a0 & !a1 & !a2 & !a3 & !a4 & !a5 & !a6 & !a7
         #  a0 &  a1 &  a3 & !a4 & !a5 & !a6 & !a7
         # !a0 &  a2 & !a4 & !a5 & !a6 & !a7 &  _X002
         # !_LC006 &  _X001;
  _X002  = EXP(!a1 & !a3);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~810~1' 
-- Equation name is '~810~1', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ010 $  _EQ011);
  _EQ010 =  a0 & !a1 & !a4 & !a5 & !a6 & !a7
         # !a2 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a2 & !a3 & !a4 & !a5 & !a6 & !a7
         #  a0 & !a3 & !a4 & !a5 & !a6 & !a7;
  _EQ011 =  _LC005 &  _X001;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~861~1' 
-- Equation name is '~861~1', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ012 $  VCC);
  _EQ012 = !a0 &  a1 & !a2 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a0 &  a1 &  a2 & !a4 & !a5 & !a6 & !a7
         # !a1 & !a3 & !a4 & !a5 & !a6 & !a7 &  _X003
         # !_LC020 &  _X001;
  _X003  = EXP( a0 &  a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~912~1' 
-- Equation name is '~912~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ013 $  _EQ014);
  _EQ013 =  a1 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a2 &  a3 & !a4 & !a5 & !a6 & !a7
         # !a0 &  a1 & !a4 & !a5 & !a6 & !a7
         # !a0 &  a3 & !a4 & !a5 & !a6 & !a7;
  _EQ014 =  _LC025 &  _X001;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~963~1' 
-- Equation name is '~963~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ015 $  VCC);
  _EQ015 =  a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a0 &  a1 & !a3 & !a4 & !a5 & !a6 & !a7
         # !a2 & !a3 & !a4 & !a5 & !a6 & !a7
         # !_LC017 &  _X001;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1014~1' 
-- Equation name is '~1014~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ016 $  VCC);
  _EQ016 =  a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7
         #  a0 &  a1 & !a2 &  a3 & !a4 & !a5 & !a6 & !a7
         # !a1 & !a3 & !a4 & !a5 & !a6 & !a7 &  _X003
         # !_LC008 &  _X001;
  _X003  = EXP( a0 &  a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1033~1~2' 
-- Equation name is '~1033~1~2', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ017 $  GND);
  _EQ017 =  a0 &  a1 &  a2 & !a3 & !a4 & !a5 & !a6 & !a7 & !_LC019
         # !a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7 & !_LC019
         #  a0 & !a1 & !a2 & !a3 & !a4 & !a5 & !a6 & !a7 & !_LC019
         # !_LC019 &  _X001
         # !en & !_LC019;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1033~1' 
-- Equation name is '~1033~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ018 $  VCC);
  _EQ018 =  a0 &  a1 &  a2 & !a3 & !a4 & !a5 & !a6 & !a7 &  en
         # !a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7 &  en
         #  a0 & !a1 & !a2 & !a3 & !a4 & !a5 & !a6 & !a7 &  en
         #  en & !_LC019 &  _X001
         #  _LC018;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1039~1' 
-- Equation name is '~1039~1', location is LC006, type is buried.
-- synthesized logic cell 
_LC006   = LCELL( _EQ019 $  GND);
  _EQ019 =  en &  _LC016
         # !en &  _LC006
         #  _LC006 &  _LC016;

-- Node name is '~1045~1' 
-- Equation name is '~1045~1', location is LC005, type is buried.
-- synthesized logic cell 
_LC005   = LCELL( _EQ020 $  GND);
  _EQ020 =  en &  _LC002
         # !en &  _LC005
         #  _LC002 &  _LC005;

-- Node name is '~1051~1~2' 
-- Equation name is '~1051~1~2', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ021 $  GND);
  _EQ021 = !a0 &  a1 & !a2 &  a3 & !a4 & !a5 & !a6 & !a7 & !_LC020
         #  a0 &  a2 & !a3 & !a4 & !a5 & !a6 & !a7 &  en &  _X003
         #  a0 &  a1 &  a2 & !a4 & !a5 & !a6 & !a7 & !_LC020
         # !a1 & !a3 & !a4 & !a5 & !a6 & !a7 & !_LC020 &  _X003
         # !_LC020 &  _X001;
  _X003  = EXP( a0 &  a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1051~1~3' 
-- Equation name is '~1051~1~3', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ022 $  GND);
  _EQ022 = !en & !_LC020
         #  _LC022;

-- Node name is '~1051~1' 
-- Equation name is '~1051~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ023 $  VCC);
  _EQ023 = !a0 &  a1 & !a2 &  a3 & !a4 & !a5 & !a6 & !a7 &  en
         #  a0 &  a1 &  a2 & !a4 & !a5 & !a6 & !a7 &  en
         # !a1 & !a3 & !a4 & !a5 & !a6 & !a7 &  en &  _X003
         #  en & !_LC020 &  _X001
         #  _LC021;
  _X003  = EXP( a0 &  a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1057~1~2' 
-- Equation name is '~1057~1~2', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ024 $  GND);
  _EQ024 =  a3 & !a4 & !a5 & !a6 & !a7 &  _LC025 &  _X004
         # !a0 &  a1 & !a4 & !a5 & !a6 & !a7 &  _LC025
         #  _LC025 &  _X001;
  _X004  = EXP( a0 & !a1 & !a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1057~1' 
-- Equation name is '~1057~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ025 $  GND);
  _EQ025 =  a3 & !a4 & !a5 & !a6 & !a7 &  en &  _X004
         # !a0 &  a1 & !a4 & !a5 & !a6 & !a7 &  en
         #  en &  _LC025 &  _X001
         # !en &  _LC025
         #  _LC023;
  _X004  = EXP( a0 & !a1 & !a2);
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1063~1~2' 
-- Equation name is '~1063~1~2', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ026 $  GND);
  _EQ026 =  a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7 & !_LC017
         #  a0 &  a1 & !a3 & !a4 & !a5 & !a6 & !a7 & !_LC017
         # !a2 & !a3 & !a4 & !a5 & !a6 & !a7 & !_LC017
         # !_LC017 &  _X001
         # !en & !_LC017;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1063~1' 
-- Equation name is '~1063~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ027 $  VCC);
  _EQ027 =  a0 & !a1 &  a2 &  a3 & !a4 & !a5 & !a6 & !a7 &  en
         #  a0 &  a1 & !a3 & !a4 & !a5 & !a6 & !a7 &  en
         # !a2 & !a3 & !a4 & !a5 & !a6 & !a7 &  en
         #  en & !_LC017 &  _X001
         #  _LC027;
  _X001  = EXP(!a4 & !a5 & !a6 & !a7);

-- Node name is '~1069~1' 
-- Equation name is '~1069~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ028 $  GND);
  _EQ028 =  en &  _LC001
         # !en &  _LC008
         #  _LC001 &  _LC008;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs A, B
--    _X003 occurs in LABs A, B




Project Information                                           d:\mul4\led7.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,461K