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-- Company: 
-- Engineer:
--
-- Create Date:    11:20:49 04/02/08
-- Design Name:    
-- Module Name:    cal_s2 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity cal_s2 is
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s2:out std_logic_vector(12 downto 0)
		  );
end cal_s2;

architecture Behavioral of cal_s2 is

component mul16 
	port(
			mul16_in:in std_logic_vector(12 downto 0);	  --msb_lsb
			mul16_out:out std_logic_vector(12 downto 0)
			);
end component;

component mul4
	port(
			mul4_in:in std_logic_vector(12 downto 0);	  --msb_lsb
			mul4_out:out std_logic_vector(12 downto 0)
			);
end component;
signal dout7:std_logic_vector(12 downto 0);
signal dout6:std_logic_vector(12 downto 0);
signal dout5:std_logic_vector(12 downto 0);
signal dout4:std_logic_vector(12 downto 0);
signal dout3:std_logic_vector(12 downto 0);
signal dout2:std_logic_vector(12 downto 0);
signal dout1:std_logic_vector(12 downto 0);
signal dout0:std_logic_vector(12 downto 0);
signal s_mul:std_logic_vector(12 downto 0);
signal s_mul_m:std_logic_vector(12 downto 0);
signal s2_tmp:std_logic_vector(12 downto 0);
signal en_con1:std_logic;
--signal en_con:std_logic;
--signal en_con_tmp:std_logic;-----
--signal cnt:integer range 1000 downto 0;
signal n1:integer range 511 downto 0;
begin
	 s2<=s2_tmp;
	 process(clk,rst)
	 	begin
			if(rst='1')then
			s2_tmp<=(others=>'0');
			n1<=0;
			elsif(clk'event and clk='1')then
				en_con1<=en_con;	 -----
				if (en_all='1')then
						if n1=511 then
							n1<=0;
						else
							n1<=n1+1;
						end if;
					if(en_init='1')then
						s2_tmp<=(others=>'0');
					else
						if(en_con1='1')then
							for i in 12 downto 0 loop
								s2_tmp(i)<=dout7(i) xor dout6(i) xor dout5(i) xor dout4(i) xor dout3(i) xor dout2(i) xor dout1(i) xor dout0(i) xor s_mul(i);
							end loop;
						else
							for i in 12 downto 0 loop
								s2_tmp(i)<=dout7(i) xor dout6(i)  xor s_mul_m(i);
							end loop;
						end if;
					end if;
				end if;
			end if;
	 end process;	
	
mul16_pro:
		mul16
		port map
		(	
			mul16_in=>s2_tmp,
	 		mul16_out=>s_mul
		);

mul4_pro:
		mul4
		port map
		(
		 mul4_in=>s2_tmp,
		 mul4_out=>s_mul_m
		);

	
	
process(clk,rst)
	begin
		if (rst='1')then
		 	dout7<=(others=>'0');
		 	dout6<=(others=>'0');
		 	dout5<=(others=>'0');
		 	dout4<=(others=>'0');
		 	dout3<=(others=>'0');
		 	dout2<=(others=>'0');
		 	dout1<=(others=>'0');
		 	dout0<=(others=>'0');
		elsif(clk'event and clk='1')then
			if(en_all='1')then
			if(en_con='1')then 
if din(7)='1' then
    dout7<="0000000110110";
else
    dout7<=(others=>'0');
end if;
if din(6)='1' then
    dout6<="1000000000000";
else
    dout6<=(others=>'0');
end if;
if din(5)='1' then
    dout5<="0010000000000";
else
    dout5<=(others=>'0');
end if;
if din(4)='1' then
    dout4<="0000100000000";
else
    dout4<=(others=>'0');
end if;
if din(3)='1' then
    dout3<="0000001000000";
else
    dout3<=(others=>'0');
end if;
if din(2)='1' then
    dout2<="0000000010000";
else
    dout2<=(others=>'0');
end if;
if din(1)='1' then
    dout1<="0000000000100";
else
    dout1<=(others=>'0');
end if;
if din(0)='1' then
    dout0<="0000000000001";
else
    dout0<=(others=>'0');
end if;
			else
				if din(7)='1' then
    				dout7<="0000000000100";
				else
    				dout7<=(others=>'0');
				end if;
				if din(6)='1' then
    				dout6<="0000000000001";
				else
    				dout6<=(others=>'0');
				end if;
			end if;
			end if;
		end if;
end process;

--cnt_pro:
--	process(clk,rst)
--		begin
--			if(rst='1')then
--				cnt<=0;
--			elsif(clk'event and clk='1')then
--				if (en_all='1')then
--					if cnt=512 then
--						cnt<=1;
--					else
--						cnt<=cnt+1;
--					end if;
--				end if;
--			end if;
--	end process;
--
--en_con_pro:
--	process(clk)
--		begin
--			if(clk'event and clk='1')then
--				if cnt=510 then
--					en_con<='0';
--				else
--					en_con<='1';
--				end if;
--				en_con_tmp<=en_con;
--			end if;
--	end process;

end Behavioral;