?? cell8.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:06:49 04/22/08
-- Design Name:
-- Module Name: cell8 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cell8 is
port
(
clk:in std_logic;
reset:in std_logic;
en_all:in std_logic;
en_init:in std_logic;
deg_r:in integer range 63 downto -63;
deg_q:in integer range 63 downto -63;
r:in std_logic_vector(12 downto 0);
q:in std_logic_vector(12 downto 0);
v:in std_logic_vector(12 downto 0);
u:in std_logic_vector(12 downto 0);
start:in std_logic;
stop_i:in std_logic;
deg_ro:out integer range 63 downto -63;
deg_qo:out integer range 63 downto -63;
ro:out std_logic_vector(12 downto 0);
qo:out std_logic_vector(12 downto 0);
vo:out std_logic_vector(12 downto 0);
uo:out std_logic_vector(12 downto 0);
start_o:out std_logic;
stop_o:out std_logic
);
end cell8;
architecture Behavioral of cell8 is
signal sw:std_logic; --1表示交換，0表示不交換
signal deg_r_tmp:integer range 63 downto -63;
signal deg_q_tmp:integer range 63 downto -63;
signal r_tmp:std_logic_vector(12 downto 0);
signal q_tmp:std_logic_vector(12 downto 0);
signal v_tmp:std_logic_vector(12 downto 0);
signal u_tmp:std_logic_vector(12 downto 0);
signal r_ex:std_logic_vector(12 downto 0);
signal q_ex:std_logic_vector(12 downto 0);
signal v_ex:std_logic_vector(12 downto 0);
signal u_ex:std_logic_vector(12 downto 0);
signal deg_r_ex:integer range 63 downto -63;
signal deg_q_ex:integer range 63 downto -63;
signal r_ex_ne:std_logic_vector(12 downto 0);
signal q_ex_ne:std_logic_vector(12 downto 0);
signal v_ex_ne:std_logic_vector(12 downto 0);
signal u_ex_ne:std_logic_vector(12 downto 0);
signal deg_r_ex_ne:integer range 63 downto -63;
signal deg_q_ex_ne:integer range 63 downto -63;
signal a:std_logic_vector(12 downto 0); --r最高項系數
signal b:std_logic_vector(12 downto 0); --q最高項系數
signal product_r:std_logic_vector(12 downto 0);
signal product_q:std_logic_vector(12 downto 0);
signal product_v:std_logic_vector(12 downto 0);
signal product_u:std_logic_vector(12 downto 0);
signal u_ex_ne_ne:std_logic_vector(12 downto 0);
signal q_ex_ne_ne:std_logic_vector(12 downto 0);
signal z_lead:std_logic;
signal deg_q_ex_ne_tmp:integer range 63 downto -63;
signal deg_r_ex_ne_tmp:integer range 63 downto -63;
signal start1:std_logic;
signal start2:std_logic;
component exchanger1
port
(
sw:in std_logic;
in1:in integer range 63 downto -63;
in2:in integer range 63 downto -63;
out1:out integer range 63 downto -63;
out2:out integer range 63 downto -63
);
end component;
component exchanger2
port
(
sw:in std_logic;
in1:in std_logic_vector(12 downto 0);
in2:in std_logic_vector(12 downto 0);
out1:out std_logic_vector(12 downto 0);
out2:out std_logic_vector(12 downto 0)
);
end component;
component mul_2_13
port
(
a:in std_logic_vector(12 downto 0);
b:in std_logic_vector(12 downto 0);
product:out std_logic_vector(12 downto 0)
);
end component;
begin
exchange1_pro:
exchanger1
port map
(
sw=>sw,
in1=>deg_r_tmp,
in2=>deg_q_tmp,
out1=>deg_r_ex,
out2=>deg_q_ex
);
exchange2rq_pro:
exchanger2
port map
(
sw=>sw,
in1=>r_tmp,
in2=>q_tmp,
out1=>r_ex,
out2=>q_ex
);
exchange2uv_pro:
exchanger2
port map
(
sw=>sw,
in1=>v_tmp,
in2=>u_tmp,
out1=>v_ex,
out2=>u_ex
);
mul_2_13_pro_r1:
mul_2_13
port map
(
a=>r_ex_ne,
b=>b,
product=>product_r
);
mul_2_13_pro_r2:
mul_2_13
port map
(
a=>q_ex_ne,
b=>a,
product=>product_q
);
mul_2_13_pro_v1:
mul_2_13
port map
(
a=>v_ex_ne,
b=>b,
product=>product_v
);
mul_2_13_pro_v2:
mul_2_13
port map
(
a=>u_ex_ne,
b=>a,
product=>product_u
);
step1:
process(clk,reset)
begin
if(reset='1')then
sw<='0';
deg_r_tmp<=63;
deg_q_tmp<=63;
r_tmp<=(others=>'0');
q_tmp<=(others=>'0');
v_tmp<=(others=>'0');
u_tmp<=(others=>'0');
elsif(clk'event and clk='1')then
if en_init='1'then
sw<='0';
deg_r_tmp<=63;
deg_q_tmp<=63;
r_tmp<=(others=>'0');
q_tmp<=(others=>'0');
v_tmp<=(others=>'0');
u_tmp<=(others=>'0');
elsif en_all='1'then
if deg_r<deg_q then
sw<='1';
else
sw<='0';
end if;
r_tmp<=r;
q_tmp<=q;
v_tmp<=v;
u_tmp<=u;
deg_r_tmp<=deg_r;
deg_q_tmp<=deg_q;
end if;
end if;
end process;
step2:
process(clk,reset)
begin
if(reset='1')then
r_ex_ne<=(others=>'0');
q_ex_ne<=(others=>'0');
v_ex_ne<=(others=>'0');
u_ex_ne<=(others=>'0');
deg_q_ex_ne<=63;
deg_r_ex_ne<=63;
a<=(others=>'0');
b<=(others=>'0');
elsif(clk'event and clk='1')then
if en_init='1' then
r_ex_ne<=(others=>'0');
q_ex_ne<=(others=>'0');
v_ex_ne<=(others=>'0');
u_ex_ne<=(others=>'0');
deg_q_ex_ne<=63;
deg_r_ex_ne<=63;
a<=(others=>'0');
b<=(others=>'0');
elsif en_all='1'then
deg_q_ex_ne<=deg_q_ex;
deg_r_ex_ne<=deg_r_ex;
r_ex_ne<=r_ex;
q_ex_ne<=q_ex;
v_ex_ne<=v_ex;
u_ex_ne<=u_ex;
if start1='0'then
--if start='0'then ----if start1='0'then 是start還是start1有待確定
a<=r_ex;
b<=q_ex;
end if;
end if;
end if;
end process;
step3:
process(start1,b)
begin
if en_all='1'then
if (start1='1' and b="0000000000000") then
z_lead<='1';
else
z_lead<='0';
end if;
end if;
end process;
process(deg_q_ex_ne,deg_r_ex_ne,z_lead,en_init)
begin
if en_init='1' then
deg_q_ex_ne_tmp<=63;
deg_r_ex_ne_tmp<=63;
elsif en_all='1'then
if z_lead='1' then
deg_q_ex_ne_tmp<=deg_q_ex_ne-1;
deg_r_ex_ne_tmp<=deg_r_ex_ne;
else
deg_r_ex_ne_tmp<=deg_r_ex_ne-1;
deg_q_ex_ne_tmp<=deg_q_ex_ne;
end if;
end if;
end process;
process(deg_r_ex_ne_tmp,deg_q_ex_ne_tmp,start1,reset,en_init) ------
begin
if reset='1'then
stop_o<='0';
elsif en_init='1'then ------
stop_o<='0'; --------
elsif start1='0' then
stop_o<='0';
elsif (deg_r_ex_ne_tmp>=10 and deg_q_ex_ne_tmp>=10) then
stop_o<='0';
else
stop_o<='1';
end if;
end process;
process(clk,reset)
begin
if (reset='1') then
deg_ro<=63;
deg_qo<=63;
elsif(clk'event and clk='1')then
if en_init='1' then
deg_ro<=63;
deg_qo<=63;
elsif en_all='1'then
if stop_i='1' then
deg_ro<=deg_r_ex_ne;
deg_qo<=deg_q_ex_ne;
else
deg_ro<=deg_r_ex_ne_tmp;
deg_qo<=deg_q_ex_ne_tmp;
end if;
end if;
end if;
end process;
process(r_ex_ne,product_r,product_q)
begin
if stop_i='1' then ---是用stop_i還是stop
ro<=r_ex_ne;
else
ro<=product_r xor product_q;
end if;
end process;
process(v_ex_ne,product_v,product_u)
begin
if stop_i='1' then ---是用stop_i還是stop
vo<=v_ex_ne;
else
vo<=product_v xor product_u;
end if;
end process;
process(q_ex_ne,q_ex_ne_ne)
begin
if stop_i='1' then ---是用stop_i還是stop
qo<=q_ex_ne;
else
qo<=q_ex_ne_ne;
end if;
end process;
process(u_ex_ne,u_ex_ne_ne)
begin
if stop_i='1' then ---是用stop_i還是stop
uo<=u_ex_ne;
else
uo<=u_ex_ne_ne;
end if;
end process;
start_pro: ---start 低有效
process(clk,reset)
begin
if(reset='1')then
start1<='1';
start2<='1';
start_o<='1';
u_ex_ne_ne<=(others=>'0');
q_ex_ne_ne<=(others=>'0');
elsif(clk'event and clk='1')then
if en_init='1'then
start1<='1';
start2<='1';
start_o<='1';
u_ex_ne_ne<=(others=>'0');
q_ex_ne_ne<=(others=>'0');
elsif en_all='1'then
start1<=start;
start2<=start1;
start_o<=start2;
u_ex_ne_ne<=u_ex_ne;
q_ex_ne_ne<=q_ex_ne;
end if;
end if;
end process;
end Behavioral;
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