#include <stdlib.h>
#include<stdio.h>
#include <malloc.h>
#define stack_init_size 100
#define stackincrement 10
typedef struct sqstack
{
int *base;
int *top;
int stacksize;
} sqstack;
int StackInit(sqstack *s)
{
s->base=(int *)malloc(stack_init_size *sizeof(int));
if(!s->base)
return 0;
s->top=s->base;
s->stacksize=stack_init_size;
return 1;
}
int Push(sqstack *s,int e)
{
if(s->top-s->base>=s->stacksize)
{
s->base=(int *)realloc(s->base,(s->stacksize+stackincrement)*sizeof(int)); if(!s->base)
return 0;
s->top=s->base+s->stacksize;
s->stacksize+=stackincrement;
}
*(s->top++)=e;
return e;
}
int Pop(sqstack *s,int e)
{
if(s->top==s->base)
return 0;
e=*--s->top;
return e;
}
int stackempty(sqstack *s)
{
if(s->top==s->base)
{
return 1;
}
else
{
return 0;
}
}
int conversion(sqstack *s)
{
int n,e=0,flag=0;
printf("輸入要轉(zhuǎn)化的十進(jìn)制數(shù)：\n");
scanf("%d",&n);
printf("要轉(zhuǎn)化為多少進(jìn)制：\n"); scanf("%d",&flag);
printf("將十進(jìn)制數(shù)%d 轉(zhuǎn)化為%d 進(jìn)制是：\n",n,flag);
while(n)
{
Push(s,n%flag);
n=n/flag;
}
while(!stackempty(s))
{
e=Pop(s,e);
switch(e)
{
case 10: printf("A");
break;
case 11: printf("B");
break;
case 12: printf("C"); break;
case 13: printf("D"); break;
case 14: printf("E"); break;
case 15: printf("F"); break;
default: printf("%d",e); }
}
printf("\n");
return 0;
}
int main()
{
sqstack s;
StackInit(&s);
conversion(&s);
return 0;
}
標(biāo)簽：
整數(shù)
棧
基本操作
十進(jìn)制
轉(zhuǎn)化
進(jìn)制
上傳時(shí)間：
2016-12-08
上傳用戶：愛(ài)你198
基于FPGA設(shè)計(jì)的字符VGA LCD顯示實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明,通過(guò)字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進(jìn)制 mif 文件存放到單端口的 ROM IP 核中，再?gòu)腞OM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來(lái)顯示到 VGA 上，F(xiàn)PGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
標(biāo)簽：
fpga
vga
lcd
上傳時(shí)間：
2021-12-18
上傳用戶：
