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A-MAX

  • Create a 1-Wire Master with Xilinx PicoBlaze

    Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.

    標簽: PicoBlaze Create Master Xilinx

    上傳時間: 2013-11-05

    上傳用戶:a6697238

  • AstroII-EVB-F1K(A)-L144開發板用戶指南

        AstroII-EVB-F1K(A)-L144開發板用戶指南

    標簽: AstroII-EVB-F 144 開發板 用戶

    上傳時間: 2013-11-22

    上傳用戶:zhichenglu

  • Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

    Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."

    標簽: Base-Station Applications Single-Chip Transceiver

    上傳時間: 2013-11-07

    上傳用戶:songrui

  • XAPP740利用AXI互聯設計高性能視頻系統

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    標簽: XAPP 740 AXI 互聯

    上傳時間: 2013-11-14

    上傳用戶:fdmpy

  • 基于CPLD的QDPSK調制解調電路設計

    為了在CDMA系統中更好地應用QDPSK數字調制方式,在分析四相相對移相(QDPSK)信號調制解調原理的基礎上,設計了一種QDPSK調制解調電路,它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上,進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中,測試結果表明,調制電路能正確選相,解調電路輸出數據與QDPSK調制輸入數據完全一致,達到了預期的設計要求。 Abstract:  In order to realize the better application of digital modulation mode QDPSK in the CDMA system, a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase,and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

    標簽: QDPSK CPLD 調制解調 電路設計

    上傳時間: 2014-01-13

    上傳用戶:qoovoop

  • MS6701數據傳輸格式

    Byte2~Byte5 字節: 表示了儀表的測量值;高四位未使用,只使用了各字節的低四位。用BCD 碼表示的數值,從高位到低 BYTE4 BYTE17 1 - 0 BATT MAX FULL A/C F/S START1 START2 UNIT_UP UNIT_DOWN 2 - 位依次為Byte5,Byte4,Byte3,Byte2。

    標簽: 6701 MS 數據傳輸

    上傳時間: 2013-10-18

    上傳用戶:thuyenvinh

  • 回路電源式顯示電表(無電源式)

    特點 精確度0.05%滿刻度 ±1位數 顯示范圍-19999-99999可任意規劃 可直接量測直流4至20mA電流,無需另接輔助電源 尺寸小(24x48x50mm),穩定性高 分離式端子,配線容易 CE 認證 主要規格 輔助電源: None 精確度: 0.05% F.S. ±1 digit(DC) 輸入抗阻: approx. 250 ohm with 20mA input 輸入電壓降: max. DC5V with 20mA input 最大過載能力: < ±50mA 取樣時間: 2.5 cycles/sec. 顯示值范圍: -19999 - 99999 digit adjustable 歸零調整范圍: -999-999 digit adjustable 最大值調整范圍: -999-999 digit adjustable 過載顯示: " doFL " or "-doFL" 極性顯示: " 一 " for negative readings 顯示幕 : Brigh Red LEDs high 8.6mm(.338") 溫度系數 : 50ppm/℃ (0-50℃) 參數設定方式: Touch switches 記憶型式: Non-volatile E2 外殼材料: ABS 絕緣耐壓能力: 2KVac/1 min. (input/case) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) 外型尺寸: 24x48x50mm CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001

    標簽: 回路電源 電表 無電源

    上傳時間: 2013-10-09

    上傳用戶:lhuqi

  • The Linux Programming Interface - A Linux and UNIX System Programming Handbook

    The Linux Programming Interface - A Linux and UNIX System

    標簽: Programming Linux Interface Handbook

    上傳時間: 2013-11-10

    上傳用戶:asdstation

  • MAX338/MAX339的英文數據手冊

      本軟件是關于MAX338, MAX339的英文數據手冊:MAX338, MAX339   8通道/雙4通道、低泄漏、CMOS模擬多路復用器   The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.   These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.

    標簽: MAX 338 339 英文

    上傳時間: 2013-11-12

    上傳用戶:18711024007

  • 3d max 9.0中文版下載

        3dmax9.0 — 全世界最知名的3D動畫制作軟件 ,最新版本 3dmax9.0 已經于去年7月底在圣地牙哥正式發布了!3dmax9.0一直在動畫市場上占有非常重要的地位,尤其在電影特效、游戲軟件開發的領域里,discreet不斷在改造出更具強大功能與相容性的軟件來迎接這個新的視覺傳播世代。 你可以在3dmax9.0最新版中,看到3dmax9.0如何幫助設計師與動畫師更精準的掌握動畫背景與人物結構,同時呈現出每個角色震撼的生命力.。 3dmax9.0 根據包括SEGA在內用戶的要求,加強了游戲和電影特效的功能。 3dmax9.0 部分新功能如下:高級列表功能,查看和管理復雜場景。新軟件包括了新的mental ray渲染器和可視工具。對Autodesk的CAD支持更好。分布式網絡材質成型。創建現實的霧、雪、噴泉、彈著點等的質點流量系統。 3dmax9.0 新功能將包括: 高級瀏覽器,可以隨時觀看圖片文件和max文件; 復雜的場景管理器用來管理大的場景; 整合的mental ray渲染器可以渲染出非常高質量的圖片和動畫、 頂點顏色繪制(vertex color painting); design visualization tools; 支持CAD、 動力學版本是reactor 2 ; distributed network texture baking; 3dmax9.0還增加了一些材質并整合了部分舊版本中常用的材質。除此之外,3dmax9.0為mental ray渲染器增添了多種材質。包括:DGS Material(physics_phen)、Glass(physics_phen)和mental ray 總的來說3dmax9.0的功能非常強大。

    標簽: max 9.0 3d

    上傳時間: 2013-10-22

    上傳用戶:181992417

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