亚洲精品欧洲精品,久久av资源网,欧美一级二级三级蜜桃

ANALOG-Digital-Converter

Design and Analysis of Analog Filters (英).pdf

資料->【E】光盤論文->【E5】英文書籍->Design and Analysis of Analog Filters (英).pdf

標簽： Analysis Filters Design Analog

上傳時間： 2013-04-24

上傳用戶：氣溫達上千萬的
直接數字頻率合成（Direct Digital Fraquency Synthesis,即DDFS

直接數字頻率合成（Direct Digital Fraquency Synthesis,即DDFS，一般簡稱DDS）是從相位概念出發直接合成所需要波形的一種新的頻率合成技術。

標簽： Fraquency Synthesis Digital Direct

上傳時間： 2013-08-27

上傳用戶：wpt
fpga digital clock

My thesis entitled \"fpga digital clock,\" immature, to enlighten

標簽： digital clock fpga

上傳時間： 2013-08-31

上傳用戶：smallfish
Fpga Implementation Of Digital Timing Recovery In Software Radio Receiver

Fpga Implementation Of Digital Timing Recovery In Software Radio Receiver

標簽： Implementation Recovery Receiver Software

上傳時間： 2013-09-05

上傳用戶：panpanpan
Verilog Coding Style for Efficient Digital Design

In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

標簽： Efficient Verilog Digital Coding

上傳時間： 2013-11-22

上傳用戶：han_zh
[模擬和數字電子電路基礎].Agarwal.&.Lang.(2005).Foundations.of.Analog.and.Digital.Electronic.Circuits

模擬和數字電子電路基礎

標簽： Foundations Electronic Circuits Agarwal

上傳時間： 2013-11-15

上傳用戶：fdfadfs
High-Speed Digital System Design

Introduce High-Speed Digital System Design.

標簽： High-Speed Digital Design System

上傳時間： 2013-10-20

上傳用戶：gps6888
模擬IC性能的權衡模擬到數字化設計的挑戰

Abstract: Many digital devices incorporate analog circuits. For instance, microprocessors, applicationspecificintegrated circuits (ASICs), and field-programmable gate arrays (FPGAs) may have internalvoltage references, analog-to-digital converters (ADCs) or digital-to-analog converters (DACs). However,there are challenges when you integrate more analog onto a digital design. As with all things in life, inelectronics we must always trade one parameter for another, with the application dictating the propertrade-off of analog function. In this application note, we examine how the demand for economy of spaceand cost pushes analog circuits onto digital substrates, and what design challenges emerge.

標簽： 模擬IC 性能模擬數字化設計

上傳時間： 2013-11-17

上傳用戶：菁菁聆聽
D類數字輸入放大器的簡化系統設計

Abstract: This application note describes a new generation of digital-input Class D audio amplifiers that achieve high PSRRperformance, comparable to traditional analog Class D amplifiers. More importantly, these digital-input Class D amplifiersprovide additional benefits of reduced power, complexity, noise, and system cost.

標簽： 數字輸入放大器系統設計

上傳時間： 2013-12-20

上傳用戶：JIUSHICHEN
音頻數模轉換器DAC抖動的靈敏度分析

Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.

標簽： DAC 音頻數模轉換器抖動

上傳時間： 2013-10-25

上傳用戶：banyou