HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer ARRAY with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C
標簽： C8051F020
上傳時間： 2013-10-12
上傳用戶：lalalal
對于瀝青混凝土攤鋪機自動找平控制系統來說，數字式控制系統的研制是目前的一個方向。介紹了一種基于CAN總線的數字式自動找平控制系統。該系統以CAN總線作為通信方式，PWM控制信號通過C8051F040單片機內部PCA可編程計數器陣列產生，并具有結構簡單、信號穩定、實時性強、易擴展的特點。通過硬件實現和系統運行達到了比較理想的控制效果，驗證了系統的可行性。 Abstract: A digital auto-leveling control system based on CAN Bus is introduced.It uses CAN Bus as the method of communication and creates PWM signals by programmable counter ARRAY in C8051F040 microcontroller. The system is simple, stable, real-time and expansive.
上傳時間： 2013-10-09
上傳用戶：ligi201200
The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full ARRAY protection.
上傳時間： 2013-11-15
上傳用戶：fklinran
狀態機設計:8.1.1 數據類型定義語句TYPE語句的用法如下：TYPE 數據類型名IS 數據類型定義OF 基本數據類型;或TYPE 數據類型名IS 數據類型定義;TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ;TYPE week IS (sun，mon，tue，wed，thu，fri，sat) ; 8.1.1 數據類型定義語句TYPE m_state IS ( st0，st1，st2，st3，st4，st5 ) ;SIGNAL present_state，next_state : m_state ;TYPE BOOLEAN IS (FALSE，TRUE) ；TYPE my_logic IS ( '1' ，'Z' ，'U' ，'0' ) ;SIGNAL s1 : my_logic ;s1 <= 'Z' ;SUBTYPE 子類型名IS 基本數據類型RANGE 約束范圍;SUBTYPE digits IS INTEGER RANGE 0 to 9 ;
標簽： 狀態
上傳時間： 2013-11-05
上傳用戶：nem567397
The 87C576 includes two separate methods of programming theEPROM ARRAY, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上傳時間： 2013-10-21
上傳用戶：xiaozhiqban
Abstract: There are many things to consider when designing a power supply for a field-programmablegate ARRAY (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上傳時間： 2013-11-10
上傳用戶：iswlkje
VGA 是視頻圖形陣列（Video Graphics ARRAY）的簡稱，是IBM 于1987 年提出的一個使用模擬信號的圖形顯示標準。最初的VGA 標準最大只能支持640*480 分辨率的顯示器，而為了適應大屏幕的應用，視頻電氣標準化組織VESA（Video Electronics StandardsAssociation 的簡稱）將VGA 標準擴展為SVGA 標準，SVGA 標準能夠支持更大的分辨率。人們通常所說的VGA 實際上指的就是VESA 制定的SVGA 標準。(1). VGA 接口VGA 采用15 針的接口，用于顯示的接口信號主要有5 個：1 個行同步信號、1 個場同步信號以及3 個顏色信號，接口還包含自測試以及地址碼信號，一般由不同的制造商定義，主要用來進行測試及支持其它功能。
上傳時間： 2013-10-27
上傳用戶：541657925
針對物體在不同色溫光源照射下呈現偏色的現象，用FPGA實現對Bayer CCD數字相機的自動白平衡處理。根據CFA(Color Filter ARRAY)的分布特點，利用雙端口RAM(DPRAM)，實現了顏色插值與色彩空間轉換。在FPGA上設計了自動白平衡的三大電路模塊：色溫估計、增益計算和色溫校正，并連接形成一個負反饋回路，然后結合EDA設計的特點，改進了增益計算的過程，有效地抑制了色彩振蕩現象。
上傳時間： 2013-10-10
上傳用戶：ouyangmark
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate ARRAY (FPGA).
上傳時間： 2014-12-22
上傳用戶：xanxuan
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer ARRAY. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時間： 2013-10-31
上傳用戶：yy_cn
