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The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽：
synchronous
Emulating
serial
上傳時(shí)間：
2014-01-31
上傳用戶(hù)：z1191176801
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In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標(biāo)簽：
Bridge
Memory
Contr
MPC
上傳時(shí)間：
2013-10-08
上傳用戶(hù)：18711024007
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The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
標(biāo)簽：
Demonstration
3200
USB
for
上傳時(shí)間：
2014-02-27
上傳用戶(hù)：zhangzhenyu
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The P90CL301 is a highly integrated 16/32 bit micro-controller especially suitable for applications requiring lowvoltage and low power consumption. It is fully software compatible with the 68000. Furthermore, it provides bothstandard as well as advanced peripheral functions on-chip.One of these peripheral functions is the I2C bus. This report describes worked-out driver software (written in C) toprogram the P90CL301 I2C interface. It also contains interface software routines offering the user a quick start inwriting a complete I2C system application.
標(biāo)簽：
P90
301
IIC
90
上傳時(shí)間：
2014-01-06
上傳用戶(hù)：氣溫達(dá)上千萬(wàn)的
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The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標(biāo)簽：
routines
slave
I2C
87L
上傳時(shí)間：
2013-11-19
上傳用戶(hù)：shirleyYim
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I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
標(biāo)簽：
microcontro
Using
76X
LPC
上傳時(shí)間：
2013-12-30
上傳用戶(hù)：Artemis
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CAN與RS232轉(zhuǎn)換節(jié)點(diǎn)的設(shè)計(jì)與實(shí)現(xiàn)
介紹將CAN總線接口與RS232總線接口相互轉(zhuǎn)換的設(shè)計(jì)方法和2種總線電平轉(zhuǎn)換關(guān)系，實(shí)現(xiàn)CAN總線與各模塊的接口設(shè)計(jì)，制定了相應(yīng)的軟硬件設(shè)計(jì)方案，并給出軟件設(shè)計(jì)流程圖以及部分硬件設(shè)計(jì)原理圖。為CAN總線與RS232總線互聯(lián)提供了一種方法，對(duì)CAN總線與RS232總線接口設(shè)備的互聯(lián)和廣泛應(yīng)用的實(shí)現(xiàn)具有重要意義。關(guān)鍵詞：CAN總線；RS-232總線；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
標(biāo)簽：
CAN
232
RS
轉(zhuǎn)換
上傳時(shí)間：
2013-11-04
上傳用戶(hù)：leesuper
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Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標(biāo)簽：
PicoBlaze
Create
Master
Xilinx
上傳時(shí)間：
2013-11-05
上傳用戶(hù)：a6697238
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FPGA as下載教程
標(biāo)簽：
FPGA
教程
上傳時(shí)間：
2014-12-28
上傳用戶(hù)：lhw888
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XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接
The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
標(biāo)簽：
XAPP
FPGA
Bank
520
上傳時(shí)間：
2013-11-19
上傳用戶(hù)：yyyyyyyyyy
