AXI協議的文檔，介紹AMBA Advanced eXtensible Interface (AXI) Protocol
上傳時間： 2013-04-24
上傳用戶：tongda
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
目的是利用嵌入在Xilinx FPGA中的MicroBlaze核實現基于AXI總線的雙核嵌入式系統設計以及共享實現LED燈的時控.
標簽： MicroBlaze SoPC AXI 總線
上傳時間： 2014-12-30
上傳用戶：stewart·
AXI Reference Guide (AXI).pdf
上傳時間： 2013-10-29
上傳用戶：libinxny
AXI Bus Functional Model v1.1 Product Brief.pdf
上傳時間： 2015-01-01
上傳用戶：kbnswdifs
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
pg059-AXI-interconnect
標簽： AXI-interconnect 059 pgpg059-AXI-interconnect
上傳時間： 2016-05-04
上傳用戶：BLOSSOM93
總線接口的詳細介紹，可在可編程邏輯電路上實現
上傳時間： 2013-11-02
上傳用戶：ccccccc
總線接口的詳細介紹，可在可編程邏輯電路上實現
上傳時間： 2013-12-15
上傳用戶：13681659100
xilinx推出的內核，ahblite和AXI之間的接口轉換。
上傳時間： 2013-12-20
上傳用戶：china97wan
