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Addition-Wesley

  • 采用TüV認證的FPGA開發功能安全系統

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System

    標簽: FPGA 安全系統

    上傳時間: 2013-11-14

    上傳用戶:zoudejile

  • Create a 1-Wire Master with Xilinx PicoBlaze

    Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.

    標簽: PicoBlaze Create Master Xilinx

    上傳時間: 2013-11-12

    上傳用戶:大三三

  • hspice 2007下載 download

    解壓密碼:www.elecfans.com 隨著微電子技術的迅速發展以及集成電路規模不斷提高,對電路性能的設計 要求越來越嚴格,這勢必對用于大規模集成電路設計的EDA 工具提出越來越高的 要求。自1972 年美國加利福尼亞大學柏克萊分校電機工程和計算機科學系開發 的用于集成電路性能分析的電路模擬程序SPICE(Simulation Program with IC Emphasis)誕生以來,為適應現代微電子工業的發展,各種用于集成電路設計的 電路模擬分析工具不斷涌現。HSPICE 是Meta-Software 公司為集成電路設計中 的穩態分析,瞬態分析和頻域分析等電路性能的模擬分析而開發的一個商業化通 用電路模擬程序,它在柏克萊的SPICE(1972 年推出),MicroSim公司的PSPICE (1984 年推出)以及其它電路分析軟件的基礎上,又加入了一些新的功能,經 過不斷的改進,目前已被許多公司、大學和研究開發機構廣泛應用。HSPICE 可 與許多主要的EDA 設計工具,諸如Candence,Workview 等兼容,能提供許多重要 的針對集成電路性能的電路仿真和設計結果。采用HSPICE 軟件可以在直流到高 于100MHz 的微波頻率范圍內對電路作精確的仿真、分析和優化。在實際應用中, HSPICE能提供關鍵性的電路模擬和設計方案,并且應用HSPICE進行電路模擬時, 其電路規模僅取決于用戶計算機的實際存儲器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.

    標簽: download hspice 2007

    上傳時間: 2013-10-18

    上傳用戶:s363994250

  • 學習資料

    學習資料,關于C++的,Addison.Wesley寫的Effective.&.More.Effective.C

    標簽:

    上傳時間: 2014-01-11

    上傳用戶:sjyy1001

  • 介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducin

    介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.

    標簽: architecture introducin peripheral improves

    上傳時間: 2015-03-15

    上傳用戶:ccclll

  • 本書是關于設計的

    本書是關于設計的,多年來我一直從事這項工作。基本上說,從我第一次試著閱 讀《設計模式》(Gamma, Helm,Johnson & Vlissides, Addison-Wesley, 1995,通常 1 被稱作“四人幫 (Gang of Four)”或者 GOF)這本書開始。

    標簽:

    上傳時間: 2013-12-12

    上傳用戶:luopoguixiong

  • c語言編譯器

    c語言編譯器,跨平臺,4.2版本 lcc version 3.x is described in the book "A Retargetable C Compiler: Design and Implementation" (Addison-Wesley, 1995, ISBN 0-8053-1670-1). There are significant differences between 3.x and 4.x, most notably in the intermediate code. For details, see http://www.research.microsoft.com/~drh/pubs/interface4.pdf.

    標簽: c語言 編譯器

    上傳時間: 2015-04-06

    上傳用戶:jkhjkh1982

  • c語言編譯器

    c語言編譯器,3.6版本 lcc version 3.x is described in the book "A Retargetable C Compiler: Design and Implementation" (Addison-Wesley, 1995, ISBN 0-8053-1670-1). There are significant differences between 3.x and 4.x, most notably in the intermediate code. For details, see http://www.research.microsoft.com/~drh/pubs/interface4.pdf.

    標簽: c語言 編譯器

    上傳時間: 2015-04-06

    上傳用戶:小儒尼尼奧

  • VC技術內幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet techno

    VC技術內幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In addition to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.

    標簽: Microsoft continued Internet English

    上傳時間: 2013-12-08

    上傳用戶:lepoke

  • avaSoft 目前正在準備這本書。這是一本教程

    avaSoft 目前正在準備這本書。這是一本教程,同時也是 JDBC 的重要參考手冊,它將作為 Java 系列的組成部份在 1997 年春季由 Addison-Wesley 出版公司出版

    標簽: avaSoft 教程

    上傳時間: 2013-12-14

    上傳用戶:lizhen9880

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