本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to Another.
Abstract: Many digital devices incorporate analog circuits. For instance, microprocessors, applicationspecificintegrated circuits (ASICs), and field-programmable gate arrays (FPGAs) may have internalvoltage references, analog-to-digital converters (ADCs) or digital-to-analog converters (DACs). However,there are challenges when you integrate more analog onto a digital design. As with all things in life, inelectronics we must always trade one parameter for Another, with the application dictating the propertrade-off of analog function. In this application note, we examine how the demand for economy of spaceand cost pushes analog circuits onto digital substrates, and what design challenges emerge.
Many applications require a clock signal to be synchronous, phase-locked, or derived fromAnother signal, such as a data signal or Another clock. This type of clock circuit is important in
氣壓是氣象監(jiān)測中的一個重要參數(shù)，提出了一種氣壓數(shù)據(jù)采集模塊設(shè)計方案，該模塊采用數(shù)字氣壓傳感器MS5534B、MSP430單片機(jī)MSP430F2272和帶實(shí)時時鐘（RTC）64 KB鐵電存儲器。通過低功耗軟件設(shè)計方法以微安級整體平均功耗實(shí)現(xiàn)了氣壓數(shù)據(jù)的采集和存儲，適合電池供電的連續(xù)高精度氣壓采集應(yīng)用。給出了模塊的軟硬件設(shè)計以及MS5534B的性能指標(biāo)和使用經(jīng)驗。
Abstract:
Air pressure is an important parameter in weather monitor.This paper futs forward a new design scheme of low power-air pressure data acquisition module.The module uses a digital output barometer sensor MS5534B,MSP430 microcontroller MSP430F2272 and integrated RTC 64KB FRAM,precision air pressure measurement and storage chip.Another point of this module is low power consumption, so it is well suited for battery powered air pressure data acquisition applications. At the same time,the software and hardware deign of module is presented,And the speciaties and use notices of MS5534B are given.
PC機(jī)之間串口通信的實(shí)現(xiàn)一、實(shí)驗?zāi)康?nbsp;１．熟悉微機(jī)接口實(shí)驗裝置的結(jié)構(gòu)和使用方法。 ２．掌握通信接口芯片8251和8250的功能和使用方法。 ３．學(xué)會串行通信程序的編制方法。
二、實(shí)驗內(nèi)容與要求 １．基本要求主機(jī)接收開關(guān)量輸入的數(shù)據(jù)（二進(jìn)制或十六進(jìn)制），從鍵盤上按“傳輸”鍵（可自行定義），就將該數(shù)據(jù)通過8251A傳輸出去。終端接收后在顯示器上顯示數(shù)據(jù)。具體操作說明如下：（１）出現(xiàn)提示信息“start with R in the board!”，通過調(diào)整乒乓開關(guān)的狀態(tài)，設(shè)置8位數(shù)據(jù)；（２）在小鍵盤上按“R”鍵，系統(tǒng)將此時乒乓開關(guān)的狀態(tài)讀入計算機(jī)I中，并顯示出來，同時顯示經(jīng)串行通訊后，計算機(jī)II接收到的數(shù)據(jù)；（３）完成后，系統(tǒng)提示“do you want to send Another data? Y/N”，根據(jù)用戶需要，在鍵盤按下“Y”鍵，則重復(fù)步驟（1），進(jìn)行另一數(shù)據(jù)的通訊；在鍵盤按除“Y”鍵外的任意鍵，將退出本程序。２．提高要求 能夠進(jìn)行出錯處理，例如采用奇偶校驗，出錯重傳或者采用接收方回傳和發(fā)送方確認(rèn)來保證發(fā)送和接收正確。
三、設(shè)計報告要求 １．設(shè)計目的和內(nèi)容 ２．總體設(shè)計 ３．硬件設(shè)計：原理圖（接線圖）及簡要說明 ４．軟件設(shè)計框圖及程序清單５．設(shè)計結(jié)果和體會（包括遇到的問題及解決的方法）
四、8251A通用串行輸入/輸出接口芯片由于CPU與接口之間按并行方式傳輸，接口與外設(shè)之間按串行方式傳輸，因此，在串行接口中，必須要有“接收移位寄存器”（串→并）和“發(fā)送移位寄存器”（并→串）。能夠完成上述“串←→并”轉(zhuǎn)換功能的電路，通常稱為“通用異步收發(fā)器”（UART：Universal Asynchronous Receiver and Transmitter）,典型的芯片有：Intel 8250/8251。8251A異步工作方式：如果8251A編程為異步方式，在需要發(fā)送字符時，必須首先設(shè)置TXEN和CTS#為有效狀態(tài)，TXEN(Transmitter Enable)是允許發(fā)送信號，是命令寄存器中的一位；CTS#(Clear To Send)是由外設(shè)發(fā)來的對CPU請求發(fā)送信號的響應(yīng)信號。然后就開始發(fā)送過程。在發(fā)送時，每當(dāng)CPU送往發(fā)送緩沖器一個字符，發(fā)送器自動為這個字符加上1個起始位，并且按照編程要求加上奇／偶校驗位以及1個、1.5個或者2個停止位。串行數(shù)據(jù)以起始位開始，接著是最低有效數(shù)據(jù)位，最高有效位的后面是奇／偶校驗位，然后是停止位。按位發(fā)送的數(shù)據(jù)是以發(fā)送時鐘TXC的下降沿同步的，也就是說這些數(shù)據(jù)總是在發(fā)送時鐘TXC的下降沿從8251A發(fā)出。數(shù)據(jù)傳輸?shù)牟ㄌ芈嗜Q于編程時指定的波特率因子，為發(fā)送器時鐘頻率的1、1/16或1/64。當(dāng)波特率指定為16時，數(shù)據(jù)傳輸?shù)牟ㄌ芈示褪前l(fā)送器時鐘頻率的1/16。CPU通過數(shù)據(jù)總線將數(shù)據(jù)送到8251A的數(shù)據(jù)輸出緩沖寄存器以后，再傳輸?shù)桨l(fā)送緩沖器，經(jīng)移位寄存器移位，將并行數(shù)據(jù)變?yōu)榇袛?shù)據(jù)，從TxD端送往外部設(shè)備。在8251A接收字符時，命令寄存器的接收允許位RxE(Receiver Enable)必須為1。8251A通過檢測RxD引腳上的低電平來準(zhǔn)備接收字符，在沒有字符傳送時RxD端為高電平。8251A不斷地檢測RxD引腳，從RxD端上檢測到低電平以后，便認(rèn)為是串行數(shù)據(jù)的起始位，并且啟動接收控制電路中的一個計數(shù)器來進(jìn)行計數(shù)，計數(shù)器的頻率等于接收器時鐘頻率。計數(shù)器是作為接收器采樣定時，當(dāng)計數(shù)到相當(dāng)于半個數(shù)位的傳輸時間時再次對RxD端進(jìn)行采樣，如果仍為低電平，則確認(rèn)該數(shù)位是一個有效的起始位。若傳輸一個字符需要16個時鐘，那么就是要在計數(shù)8個時鐘后采樣到低電平。之后，8251A每隔一個數(shù)位的傳輸時間對RxD端采樣一次，依次確定串行數(shù)據(jù)位的值。串行數(shù)據(jù)位順序進(jìn)入接收移位寄存器，通過校驗并除去停止位，變成并行數(shù)據(jù)以后通過內(nèi)部數(shù)據(jù)總線送入接收緩沖器，此時發(fā)出有效狀態(tài)的RxRDY信號通知CPU，通知CPU8251A已經(jīng)收到一個有效的數(shù)據(jù)。一個字符對應(yīng)的數(shù)據(jù)可以是5～8位。如果一個字符對應(yīng)的數(shù)據(jù)不到8位，8251A會在移位轉(zhuǎn)換成并行數(shù)據(jù)的時候，自動把他們的高位補(bǔ)成0。
五、系統(tǒng)總體設(shè)計方案根據(jù)系統(tǒng)設(shè)計的要求，對系統(tǒng)設(shè)計的總體方案進(jìn)行論證分析如下：1．獲取8位開關(guān)量可使用實(shí)驗臺上的8255A可編程并行接口芯片，因為只要獲取8位數(shù)據(jù)量，只需使用基本輸入和8位數(shù)據(jù)線，所以將8255A工作在方式0，PA0-PA7接實(shí)驗臺上的8位開關(guān)量。2．當(dāng)使用串口進(jìn)行數(shù)據(jù)傳送時，雖然同步通信速度遠(yuǎn)遠(yuǎn)高于異步通信，可達(dá)500kbit/s，但由于其需要有一個時鐘來實(shí)現(xiàn)發(fā)送端和接收端之間的同步，硬件電路復(fù)雜，通常計算機(jī)之間的通信只采用異步通信。3．由于8251A本身沒有時鐘，需要外部提供，所以本設(shè)計中使用實(shí)驗臺上的8253芯片的計數(shù)器2來實(shí)現(xiàn)。4：顯示和鍵盤輸入均使用DOS功能調(diào)用來實(shí)現(xiàn)。設(shè)計思路框圖，如下圖所示：
六、硬件設(shè)計硬件電路主要分為8位開關(guān)量數(shù)據(jù)獲取電路，串行通信數(shù)據(jù)發(fā)送電路，串行通信數(shù)據(jù)接收電路三個部分。1．8位開關(guān)量數(shù)據(jù)獲取電路該電路主要是利用8255并行接口讀取8位乒乓開關(guān)的數(shù)據(jù)。此次設(shè)計在獲取8位開關(guān)數(shù)據(jù)量時采用8255令其工作在方式0，A口輸入8位數(shù)據(jù)，CS#接實(shí)驗臺上CS1口，對應(yīng)端口為280H-283H，PA0-PA7接8個開關(guān)。2．串行通信電路串行通信電路本設(shè)計中8253主要為8251充當(dāng)頻率發(fā)生器，接線如下圖所示。
The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message selected at Another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our customers, we must be able to support alltheir interface requirements. For us to be able to make products for many customers, we mustadopt a modular approach to the design. This modularity is the one issue that drives the majorproblem of shifting our bits from one modular interface to Another.
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message selected at Another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.
