The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
上傳時間： 2014-12-28
上傳用戶：270189020
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上傳時間： 2013-10-13
上傳用戶：bakdesec
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時間： 2013-10-11
上傳用戶：dianxin61
提出了一個由AT89C52單片機控制步進電機的實例?？梢酝ㄟ^鍵盤輸入相關數據, 并根據需要, 實時對步進電機工作方式進行設置, 具有實時性和交互性的特點。該系統可應用于步進電機控制的大多數場合。實踐表明, 系統性能優于傳統的步進電機控制器。關鍵詞: 單片機; 步進電動機; 直流固態繼電器; 實時控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
標簽： Control System ingMot Stepp
上傳時間： 2013-11-19
上傳用戶：leesuper
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
控制
上傳時間： 2013-10-21
上傳用戶：風行天下
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
在Multisim 10軟件環境下，設計一種由運算放大器構成的精確可控矩形波信號發生器，結合系統電路原理圖重點闡述了各參數指標的實現與測試方法。通過改變RC電路的電容充、放電路徑和時間常數實現了占空比和頻率的調節，通過多路開關投入不同數值的電容實現了頻段的調節，通過電壓取樣和同相放大電路實現了輸出電壓幅值的調節并提高了電路的帶負載能力，可作為頻率和幅值可調的方波信號發生器。Multisim 10仿真分析及應用電路測試結果表明，電路性能指標達到了設計要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上傳時間： 2014-01-21
上傳用戶：shen007yue
