Designand Analysisof Fast Text Compression Basedon Quasi-Arithmetic Coding.
標(biāo)簽： Quasi-Arithmetic Compression Analysisof Designand
上傳時(shí)間： 2013-12-11
上傳用戶：kelimu
Galois Field Arithmetic algorithm
標(biāo)簽： Arithmetic algorithm Galois Field
上傳時(shí)間： 2014-12-21
上傳用戶：685
H.264/AVC是ITU與ISO/IEC(International Standard Organization/Intemational Electrotechnical Commission國際標(biāo)準(zhǔn)化組織/國際電工委員會(huì))聯(lián)合推出的活動(dòng)圖像編碼標(biāo)準(zhǔn)。作為最新的國際視頻編碼標(biāo)準(zhǔn)，H.264/AVC與MPEG-4、H.263等視頻編碼標(biāo)準(zhǔn)相比，性能有了很大提高，并已在流媒體、數(shù)字電視、電話會(huì)議、視頻存儲(chǔ)等諸多領(lǐng)域得到廣泛的應(yīng)用。基于上下文的自適應(yīng)二進(jìn)制算術(shù)編碼(Conrext-based Adaptive Binary Arithmetic Coding，CABAC)是H.264/AVC的兩個(gè)熵編碼方案之一，相對(duì)于另一熵編碼方案-CAVLC(基于上下文的自適應(yīng)可變長編碼)，CABAC具有更高的數(shù)據(jù)壓縮率：在同等編碼質(zhì)量下要比CAVLC提高10％～15％的壓縮率。CABAC能實(shí)現(xiàn)很高的數(shù)據(jù)壓縮率，但這是以增加實(shí)現(xiàn)的復(fù)雜性為代價(jià)的。在已有的硬件實(shí)現(xiàn)方法上，CABAC的解碼效率并不高。 論文在深入研究CABAC解碼算法及其實(shí)現(xiàn)流程，并在仔細(xì)分析了H.264/AVC碼流結(jié)構(gòu)的基礎(chǔ)上，總結(jié)出了影響CABAC解碼效率的各個(gè)環(huán)節(jié)，并以此為出發(fā)點(diǎn)，對(duì)CABAC解碼所需中的各個(gè)功能模塊進(jìn)行了優(yōu)化設(shè)計(jì)，設(shè)計(jì)出一種新的CABAC解碼器結(jié)構(gòu)，相對(duì)于一般的CABAC解碼器，它的解碼效率得到了顯著提高。論文針對(duì)影響CABAC解碼過程的"瓶頸"問題一多次訪問存儲(chǔ)部件影響解碼速率，提出了新的存儲(chǔ)組織方式，并根據(jù)CABAC的碼流結(jié)構(gòu)特性，采用4個(gè)子解碼器級(jí)聯(lián)的方式來進(jìn)一步提高解碼速率。 最后，用Verilog語言對(duì)所設(shè)計(jì)的CABAC解碼器進(jìn)行了描述，用EDA軟件對(duì)其進(jìn)行了仿真，并在FPGA上驗(yàn)證了其功能，結(jié)果顯示，該CABAC解碼器結(jié)構(gòu)顯著提高了解碼效率，能夠滿足高檔次實(shí)時(shí)通訊的要求。
上傳時(shí)間： 2013-07-03
上傳用戶：huazi
Abstract: This application note describes how to improve the speed of modular exponentiation by more than 50% whenusing MAXQ® microcontrollers that have a modular Arithmetic accelerator (MAA).
標(biāo)簽： 如何提高 模冪運(yùn)算 應(yīng)用筆記 速度
上傳時(shí)間： 2013-11-17
上傳用戶：s363994250
基于單DSP的VoIP模擬電話適配器研究與實(shí)現(xiàn):提出和實(shí)現(xiàn)了一種新穎的基于單個(gè)通用數(shù)字信號(hào)處理器(DSP)的VoIP模擬電話適配器方案。DSP的I/O和存儲(chǔ)資源非常有限，通常適于運(yùn)算密集型應(yīng)用，不適宜控制密集型應(yīng)用[5]。該系統(tǒng)高效利用單DSP的I/O和片內(nèi)外存儲(chǔ)器資源，采用μC/OS-II嵌入式實(shí)時(shí)操作系統(tǒng)，支持SIP和TCP-UDP/IP協(xié)議，通過LAN或者寬帶接入，使普通電話機(jī)成為Internet終端，實(shí)現(xiàn)IP電話。該系統(tǒng)軟硬件結(jié)構(gòu)緊湊高效，運(yùn)行穩(wěn)定，成本低，具有廣闊的應(yīng)用前景。關(guān)鍵詞：模擬電話適配器；IP電話；數(shù)字信號(hào)處理器；μC/OS-II 【Abstract】This paper presents a VoIP ATA solution based on a single digital signal processor (DSP). DSPs are suitable for Arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal processor (DSP); μC/OS-II Research and Implementation of VoIPATA Based on Single DSP
上傳時(shí)間： 2013-11-20
上傳用戶：Wwill
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II Arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時(shí)間： 2013-10-12
上傳用戶：kang1923
很好用的壓縮和解壓縮程序，Arithmetic，請(qǐng)大家試用一下，多指教！
上傳時(shí)間： 2015-03-19
上傳用戶：ruixue198909
In each step the LZSS algorithm sends either a character or a <position, length> pair. Among these, perhaps character "e" appears more frequently than "x", and a <position, length> pair of length 3 might be commoner than one of length 18, say. Thus, if we encode the more frequent in fewer bits and the less frequent in more bits, the total length of the encoded text will be diminished. This consideration suggests that we use Huffman or Arithmetic coding, preferably of adaptive kind, along with LZSS.
標(biāo)簽： algorithm character position either
上傳時(shí)間： 2014-01-27
上傳用戶：wang0123456789
vhdl程序源代碼，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等
上傳時(shí)間： 2013-12-26
上傳用戶：363186
/* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm
標(biāo)簽： generates the program define
上傳時(shí)間： 2015-07-07
上傳用戶：wangchong
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