cordic IC implement for fast cordic calculate. Including test BENCH. feature: 1. slicon proved. 2. support angle recored algorithm.
標簽： cordic calculate Including implement
上傳時間： 2017-01-06
上傳用戶：270189020
test BENCH for spi communication
標簽： communication BENCH test for
上傳時間： 2017-04-25
上傳用戶：zm7516678
TEst BENCH of an increment date
上傳時間： 2017-04-27
上傳用戶：colinal
Test BENCH for an engine code VHDL for CY7C1062AV33
上傳時間： 2017-04-27
上傳用戶：tfyt
Test BENCH for CY7C1062AV33
上傳時間： 2014-12-07
上傳用戶：lingzhichao
Pure hardware JPEG Encoder design. Package includes vhdl source code, test BENCH, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
標簽： design hardware includes Encoder
上傳時間： 2013-12-15
上傳用戶：王者A
怎樣編寫仿真功能的測試文件（test BENCH）
上傳時間： 2014-11-17
上傳用戶：磊子226
介紹一種基于C8051F060單片機和NAND Flash的數據采集存儲系統，該系統可實現3路信號采樣，每路采樣率為5KS/s,通過異步串行通信接口實現數據傳輸。并詳細說明系統的軟件設計。 Abstract: An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to sample three-channel of signal,5KSPS each channel,and can upload data to test BENCH through UART（Universal Asynchronous Receiver/Transmitter）.The software design is discussed in detail.
上傳時間： 2013-10-12
上傳用戶：Jesse_嘉偉
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL TestBENCH files. This files only include the testBENCH behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test BENCH for txmit.vhd. rcvr_tf.vhd -- Test BENCH for rcvr.vhd.
上傳時間： 2013-11-07
上傳用戶：jasson5678
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL TestBENCH files. This files only include the testBENCH behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test BENCH for txmit.vhd. rcvr_tf.vhd -- Test BENCH for rcvr.vhd.
上傳時間： 2013-11-02
上傳用戶：18862121743
