This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-BIt data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
標(biāo)簽： applications development hardware paper
上傳時(shí)間： 2013-12-21
上傳用戶：jichenxi0730
forming of a signal, GLONASS system, coherent reception, graph autocorrelation, crosscorrelation function, BIt-error probability[SNR]
標(biāo)簽： crosscorrelation autocorrelation reception coherent
上傳時(shí)間： 2013-12-27
上傳用戶：小鵬
Embedded System Design using 8031 microcontroller defines many steps in development of embedded systems using the most popular 8-BIt microcontroller using various examples. I hope this would be useful to everyone.
標(biāo)簽： microcontroller development Embedded embedded
上傳時(shí)間： 2017-04-02
上傳用戶：lnnn30
200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • Linux® , Microsoft® Windows® CE-enabled MMU • 100-MHz System Bus • MaverickCrunch™ Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey™ IDs • 32-BIt Unique ID can be used for DRM-compliant 128-BIt random ID. • Integrated Peripheral Interfaces • 32-BIt SDRAM Interface
標(biāo)簽： 8226 Cache kbyte Instruction
上傳時(shí)間： 2017-04-08
上傳用戶：comua
使用FPGA/CPLD設(shè)置語(yǔ)音AD、DA轉(zhuǎn)換芯片AIC23，F(xiàn)PGA/CPLD系統(tǒng)時(shí)鐘為24.576MHz 1、AIC系統(tǒng)時(shí)鐘為12.288MHz，SPI時(shí)鐘為6.144MHz 2、AIC處于主控模式 3、input BIt length 16BIt output BIt length 16BIt MSB first 4、幀同步在96KHz
上傳時(shí)間： 2013-12-20
上傳用戶：二驅(qū)蚊器
Here are the functions for Hamming code 7.4 and Extended Hamming code 8.4 encoding and decoding. For 7.4 code, one error per 7-BIt codeword can be corrected. For 8.4 code, one error per 8-BIt codeword can be corrected and not less than 2 errors can be detected.
標(biāo)簽： Hamming code and functions
上傳時(shí)間： 2014-01-05
上傳用戶：Amygdala
A combined space鈥搕ime block coding (STBC) and eigen-space tracking (EST) scheme in multiple-input-multiple-output systems is proposed. It is proved that the STBC-EST is capable of shifting hardware complexity from the receiver to the transmitter without any BIt error rate (BER) performance loss. A computation efficient EST algorithm is also proposed, which makes the STBC-EST affordable. Simulation results show that the STBC-EST with a modest feedback requirement results in a negligible BER performance loss compared with a dual system configuration.
標(biāo)簽： multiple-input-m eigen-space combined tracking
上傳時(shí)間： 2014-01-13
上傳用戶：磊子226
SCSI Multimedia Commands 鈥?2 (MMC-2) NCITS 333 T10/1228-D 4.1.1. CD address reporting formats (MSF BIt) Several CD commands can report addresses either in logical block address or in MSF format (see Table 1). The READ HEADER, READ SUB-CHANNEL, and READ TOC/PMA/ATIP commands have this Feature
標(biāo)簽： Multimedia reporting Commands address
上傳時(shí)間： 2013-12-21
上傳用戶：lepoke
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-BIt Wishbone slave bus interface. – FIFO depth configurable via paramters.
標(biāo)簽： speed USBHostSlave and Supports
上傳時(shí)間： 2014-01-17
上傳用戶：sxdtlqqjl
This program implements a PIC-based fuzzy inference engine for the Fudge fuzzy development system from Motorola. It works by taking the output from Fudge for the 68HC11 processor, and converting it to a MPASM compatible assembler file using the convert batch file. This file can then be incorporated with fuzzy.asm to create a fuzzy inference engine. Tool chain ---------- FUDGE -> Fuzzy Rules -> MC68HC11.ASM -> CONVERT.BAT -> RULES.ASM -> MPASM FUZZY.ASM -> INTEL HEX Fuzzy input registers --------------------- current_ins 1..8 x 8-BIt raw inputs Fuzzy inference function ------------------------ FuzzyEngine Fuzzy output registers ---------------------- cog_outs 1..8 x 8-BIt raw outputs
標(biāo)簽： fuzzy development implements PIC-based
上傳時(shí)間： 2014-01-18
上傳用戶：caozhizhi
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