個人認為幾個比較實用的VHDL源碼之二——Behavioural model of a simple 8-bit CPU
標簽： Behavioural simple model VHDL
上傳時間： 2013-12-16
上傳用戶：gdgzhym
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標簽： entity-architectures Multiplier contains complete
上傳時間： 2015-07-02
上傳用戶：2467478207
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable
標簽： continous IDCT-M accept medium
上傳時間： 2015-07-07
上傳用戶：1583060504
empirical mode decomposition(EMD)分解算法的matlab代碼
標簽： decomposition empirical matlab mode
上傳時間： 2013-11-28
上傳用戶：小眼睛LSL
11 bit dsp core data sheet
上傳時間： 2013-12-13
上傳用戶：Avoid98
TigerSharc TS201 32-bit floating point FFT routine
標簽： TigerSharc floating routine point
上傳時間： 2015-07-23
上傳用戶：小眼睛LSL
TigerSharc TS201 32-bit floating point IIR filter routine.
標簽： TigerSharc floating routine filter
上傳時間： 2014-01-21
上傳用戶：tyler
zemax源碼： This DLL models a standard ZEMAX surface type, either plane, sphere, or conic The surface also demonstrates a user-defined apodization filter The filter is defined as part of the real ray trace, case 5 The filter can be used at the stop to produce x-y Gaussian apodization similar to the Gaussian pupil apodization in ZEMAX but separate in x and y. The amplitude apodization is of the form EXP[-(Gx(x/R)^2 + Gy(y/R)^2)] The transmission is of the form EXP[-2(Gx(x/R)^2 + Gy(y/R)^2)] where x^2 + y^2 = r^2 R = semi-diameter The tranmitted intensity is maximum in the center. T is set to 0 if semi-diameter < 1e-10 to avoid division by zero.
標簽： standard surface models either
上傳時間： 2013-12-05
上傳用戶：003030
通過奇異值分解實現的最小二乘擬合算法 inear least-squares fit by singular value decomposition
標簽： decomposition least-squares singular inear
上傳時間： 2015-07-26
上傳用戶：bibirnovis
verilog 32-bit ALU
上傳時間： 2013-12-18
上傳用戶：yulg
