A 64 sub carrier OFDM system based on the parameter of Mean square error
標簽： parameter carrier square system
上傳時間： 2013-12-27
上傳用戶：yyq123456789
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410A
上傳時間： 2013-11-30
上傳用戶：GavinNeko
calculator for calculating interest rate in a mobile phone
標簽： calculating calculator interest mobile
上傳時間： 2017-06-16
上傳用戶：zjf3110
bit torrent protocol in pdf
上傳時間： 2014-01-16
上傳用戶：czl10052678
LCD using 4 bit mode on a s08 (make sure to adjust delay for faster clocks, ie make delay longer)
上傳時間： 2014-11-29
上傳用戶：cccole0605
vhdl source code for 8 bit datapath logic
標簽： datapath source logic vhdl
上傳時間： 2013-12-15
上傳用戶：開懷常笑
Samsung 8-bit machine the realization of the definition and operation of the sample file spaces
標簽： the realization definition operation
上傳時間： 2013-11-29
上傳用戶：aeiouetla
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
標簽： Wishbone Supports includes Low-Pin
上傳時間： 2014-12-20
上傳用戶：古谷仁美
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
標簽： Consecutive Description AES Features
上傳時間： 2017-06-25
上傳用戶：talenthn
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.
標簽： implementation twofish cipher VHDL
上傳時間： 2017-06-25
上傳用戶：王小奇
