This manual describes SAMSUNG s S3C2410A 16/32-Bit RISC microprocessor. This product is designed to provide
hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller
solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate
16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT),
NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch
Timers with PWM, I/O Ports, RTC, 8-ch 10-Bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS
Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽：
This
microprocessor
describes
S3C2410A
上傳時間：
2013-11-30
上傳用戶：GavinNeko
VHDL implementation of the twofish cipher for 128,192 and 256 Bit keys.
The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 Bit key sizes, along with their respective vector files.
標簽：
implementation
twofish
cipher
VHDL
上傳時間：
2017-06-25
上傳用戶：王小奇
