opencore ahb to wishbone bus verilog code
標簽： opencore wishbone verilog code
上傳時間： 2013-12-07
上傳用戶：努力努力再努力
Universal Serial Bus 3.0 Specification,USB3.0新規格SPEC希望對研究USB3.0的人有幫助.
標簽： 3.0 Specification Universal USB
上傳時間： 2014-01-05
上傳用戶：wys0120
GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface
標簽： microprocessor programmable tri-state General
上傳時間： 2017-06-13
上傳用戶：hxy200501
Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.
標簽： address addressin indirect Jh_cpu
上傳時間： 2017-06-14
上傳用戶：bakdesec
LLRF CONTROL SYSTEM USING A COMMERCIAL BOARD for PCI BUS capture date
標簽： COMMERCIAL CONTROL capture SYSTEM
上傳時間： 2013-12-16
上傳用戶：CHENKAI
The SL11RIDE is a low cost, high speed Universal Serial Bus RISC based Controller board. It contains a 16-bit RISC processor with built in SL11RIDE ROM to greatly reduce firmware development efforts. Its serial flash EEPROM interface offers low cost storage for USB device configuration and customer product specific functions. New functions can be programmed into the I2C by downloading it from a USB Host PC. This unique architecture provides the ability to upgrade products, in the field, without changing the peripheral hardware.
標簽： Controller Universal contains Serial
上傳時間： 2014-01-06
上傳用戶：15071087253
This file contains routines to write to and read from the I2C bus using the GPIO pins of the CS5530.
標簽： the contains routines write
上傳時間： 2014-01-21
上傳用戶：zaizaibang
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
標簽： Tensilica OpenCores interface the
上傳時間： 2013-12-21
上傳用戶：gonuiln
pci pci轉local bus總線的應用，使用IPcore alter器件
上傳時間： 2013-12-28
上傳用戶：二驅蚊器
Meter Bus protocol specification
標簽： specification protocol Meter Bus
上傳時間： 2013-12-20
上傳用戶：lacsx
