This reference design describes the design of a 3-phase AC induction vector control drive with position encoder coupled to the motor shaft. It is based on Motorola’s DSP56F805 dedicated motor control device. AC induction motors, which contain a cage, are very popular in variable speed drives. They are simple, rugged, inexpensive and available at all power ratings. Progress in the field of power electronics and microelectronics enables the application of induction motors for high-performance drives, where traditionally only DC motors were applied. Thanks to sophisticated control methods, AC induction drives offer the same control capabilities as high performance four-quadrant DC drives.
標簽： Reference Designer Manual Phase DRM 023 AC
上傳時間： 2020-06-10
上傳用戶：shancjb
The main aim of this book is to present a unified, systematic description of basic and advanced problems, methods and algorithms of the modern con- trol theory considered as a foundation for the design of computer control and management systems. The scope of the book differs considerably from the topics of classical traditional control theory mainly oriented to the needs of automatic control of technical devices and technological proc- esses. Taking into account a variety of new applications, the book presents a compact and uniform description containing traditional analysis and op- timization problems for control systems as well as control problems with non-probabilistic models of uncertainty, problems of learning, intelligent, knowledge-based and operation systems – important for applications in the control of manufacturing processes, in the project management and in the control of computer systems.
上傳時間： 2020-06-10
上傳用戶：shancjb
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
標簽： 隔離
上傳時間： 2021-11-24
上傳用戶：kingwide
CHAPTER 1: THE OP AMP CHAPTER 2: OTHER LINEAR CIRCUITS CHAPTER 3: SENSORS CHAPTER 4: RF/IF CIRCUITS CHAPTER 5: FUNDAMENTALS OF SAMPLED DATA SYSTEMS CHAPTER 6: CONVERTERS CHAPTER 7: DATA CONVERTER SUPPORT CIRCUITS CHAPTER 8: ANALOG FILTERS CHAPTER 9: POWER MANAGEMENT CHAPTER 10: PASSIVE COMPONENTS CHAPTER 11: OVERVOLTAGE EFFECTS ON ANALOG INTEGRATED CIRCUITS CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES CHAPTER 13: DESIGN DEVELOPMENT TOOLS
上傳時間： 2021-12-21
上傳用戶：wangshoupeng199
The PW8205A8TS is the highest performance trench N-ch MOSFETs with extreme high cell density,which provide excellent RDSON and gate charge for most of the small power switching and loadswitch applications. The meet the RoHS and Product requirement with full function reliabilityapproved .
標簽： 8205a8
上傳時間： 2022-02-14
上傳用戶：wangshoupeng199
本文主要介紹如何在Wado設計套件中進行時序約束，原文出自 xilinx中文社區。1 Timing Constraints in Vivado-UCF to xdcVivado軟件相比于sE的一大轉變就是約束文件，5E軟件支持的是UcF（User Constraints file，而 Vivado軟件轉換到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）標準，另外集成了Xinx的一些約束標準可以說這一轉變是xinx向業界標準的靠攏。Altera從 TimeQuest開始就一直使用SDc標準，這一改變，相信對于很多工程師來說是好事，兩個平臺之間的轉換會更加容易些。首先看一下業界標準SDc的原文介紹：Synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
標簽： vivado
上傳時間： 2022-03-26
上傳用戶：
以AT89S52單片機為控制核心,采用電容降壓技術,Buck電路拓撲,PWM驅動模塊和功率器件散熱設計,通過高速的數據采集、主功率輸入輸出模塊和控制模塊,設計一種新型智能車載充電器.在充電過程中,通過負脈沖瞬間放電實現對鉛酸蓄電池的再生修復,提高電池的有效容量,延長使用壽命.該充電器體積小、速度快、效率高、可靠性好.With AT89S52 single chip computer as the control core,a new type of intelligent car-carried charger was designed by using capacitance step-down technology,Buck circuit topology,PWM driving module and power device heat dissipation design,through high-speed data acquisition,main power input and output module and control module.In the charging process,the regeneration and repair of lead-acid batteries are realized by instantaneous discharge of negative pulse,which improves the effective capacity of batteries and prolongs their service life.The charger has the advantages of small size,fast speed,high efficiency and good reliability.
標簽： 車載充電器
上傳時間： 2022-03-27
上傳用戶：
DescriptionThe IMX385LQR-C is a diagonal 8.35 mm (Type 1/2) CMOS active pixel type solid-state image sensor with a squarepixel array and 2.13 M effective pixels. This chip operates with analog 3.3 V, digital 1.2 V, and interface 1.8 V triplepower supply, and has low power consumption. High sensitivity, low dark current and no smear are achieved throughthe adoption of R, G and B primary color mosaic filters. This chip features an electronic shutter with variablecharge-integration time.(Applications: Surveillance cameras)
標簽： CMOS傳感器 IMX385LQR-C
上傳時間： 2022-06-18
上傳用戶：
The GD32F103xx device is a 32-bit general-purpose microcontroller based on the ARM?Cortex?-M3 RISC core with best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex?-M3 is a next generation processor core whichis tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.The GD32F103xx device incorporates the ARM ' Cortex?-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximumefficiency. It provides up to 3 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose
標簽： gd32f103
上傳時間： 2022-07-23
上傳用戶：aben
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上傳時間： 2013-10-10
上傳用戶：inwins
