The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU CLock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
標(biāo)簽： appropriately The endpoints following
上傳時(shí)間： 2013-12-02
上傳用戶：dianxin61
在主機(jī)上編譯后，上傳CLock，重起開發(fā)板。 在主機(jī)上編譯后，上傳CLock，重起開發(fā)板。
上傳時(shí)間： 2014-11-26
上傳用戶：xaijhqx
在主機(jī)上編譯后，上傳INT，重起開發(fā)板。 在主機(jī)上編譯后，上傳CLock，重起開發(fā)板。
上傳時(shí)間： 2016-03-20
上傳用戶：sammi
小而全的軟盤鏡像文件，原創(chuàng)！fbdisk-壞道屏蔽；CLock-時(shí)鐘顯示；支持DOS下USB，快速分區(qū)；殺進(jìn)程killer.exe gdisk-最好的分區(qū)工具，方法見fd.txt。
上傳時(shí)間： 2013-12-13
上傳用戶：playboys0
This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 CLock is set to 14 MHz.
標(biāo)簽： continuously ADC describes converted
上傳時(shí)間： 2014-01-03
上傳用戶：徐孺
NRF905驅(qū)動(dòng)代碼 // The content of this struct is nRF905 s initialize data. // CH_NO=1 433MHZ Normal Opration,No Retrans RX,TX Address is 4 Bytes // RX TX Payload Width is 32 Bytes Disable Extern CLock Fosc=16MHZ // 8 Bits CRC And enable
標(biāo)簽： initialize 905 content Normal
上傳時(shí)間： 2013-12-16
上傳用戶：lanjisu111
vhdl編寫，8b—10b 編解碼器設(shè)計(jì) Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous CLocked inputs (latched on each CLock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 CLock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous CLocked inputs (latched on each CLock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 CLock later
上傳時(shí)間： 2016-05-05
上傳用戶：gundamwzc
16位cpu設(shè)計(jì)VHDL源碼，其中包括alu，CLock，memory等部分的設(shè)計(jì)
上傳時(shí)間： 2016-06-30
上傳用戶：saharawalker
This assignment requires you to complete the dynamic drawing components of the Date/Time Control Panel from the previous two programming assignments. In particular, you will be moving the map found in the "Time Zone" tab when the time zone changes and will be drawing a CLock face corresponding to the time setting.
標(biāo)簽： assignment components the requires
上傳時(shí)間： 2016-07-03
上傳用戶：JIUSHICHEN
s3c2410平臺(tái)的開發(fā)詳解 包括 開發(fā)環(huán)境 linux的 還有 gdb的 還有基礎(chǔ)實(shí)驗(yàn) 包括LED I/O, linux, memory , flash , uart , 中斷,timer ,mmu, CLock還有bootloader vivi等 初學(xué)者的 寶典 強(qiáng)烈推薦
標(biāo)簽： linux s3c2410 memory flash
上傳時(shí)間： 2014-01-25
上傳用戶：wangyi39
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