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CORE-v

-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on s

-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues

標簽： Herveille WISHBONE compiant Richard

上傳時間： 2014-01-18

上傳用戶：tzl1975
REBOL core 請大家不要下載

REBOL core 請大家不要下載，這是為了下載別的軟件上傳的假貨，

標簽： REBOL core 家

上傳時間： 2015-07-03

上傳用戶：CSUSheep
icrocom的糾錯和壓縮協議常簡寫為MNP(Microcom Network Protocol),它由一系列獨立的糾錯和壓縮協議組成,在數據壓縮協議方面,MNP5和V.42bis最為流行。MNP5使

icrocom的糾錯和壓縮協議常簡寫為MNP(Microcom Network Protocol),它由一系列獨立的糾錯和壓縮協議組成,在數據壓縮協議方面,MNP5和V.42bis最為流行。MNP5使用了兩種壓縮算法.

標簽： MNP Microcom Protocol icrocom

上傳時間： 2013-12-31

上傳用戶：youth25
《Core Java2 Volume I-5e》源碼

《Core Java2 Volume I-5e》源碼

標簽： Volume Java2 Core 源碼

上傳時間： 2015-07-06

上傳用戶：tb_6877751
v數據結構課程設計數據結構課程設計

v數據結構課程設計數據結構課程設計

標簽： 數據結構

上傳時間： 2013-12-25

上傳用戶：liuchee
/* This program generates the DApkg.vhd file that is used to define * the DA filter core and give

/* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm

標簽： generates the program define

上傳時間： 2015-07-07

上傳用戶：wangchong
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at

IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable

標簽： continous IDCT-M accept medium

上傳時間： 2015-07-07

上傳用戶：1583060504
<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.

<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For simulation **** To run the simulation read readme.txt in folder test_bench.

標簽： vhd post_norm_addsub pre_norm_addsub Floating

上傳時間： 2014-01-18

上傳用戶：czl10052678
verilog ADPLL file with testbench.v

verilog ADPLL file with testbench.v

標簽： testbench verilog ADPLL file

上傳時間： 2015-07-09

上傳用戶：cx111111
core 24 - H.264/MPEG-4 AVC codec - Copyleft 2005 - http://www.videolan.org/x264.html

core 24 - H.264/MPEG-4 AVC codec - Copyleft 2005 - http://www.videolan.org/x264.html

標簽： 264 Copyleft videolan codec

上傳時間： 2015-07-11

上傳用戶：a673761058