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  • 基于ZigBee技術(shù)的無(wú)線智能家用燃?xì)鈭?bào)警系統(tǒng)

    在研究傳統(tǒng)家用燃?xì)鈭?bào)警器的基礎(chǔ)上,以ZigBee協(xié)議為平臺(tái),構(gòu)建mesh網(wǎng)狀網(wǎng)絡(luò)實(shí)現(xiàn)網(wǎng)絡(luò)化的智能語(yǔ)音報(bào)警系統(tǒng)。由于傳感器本身的溫度和實(shí)際環(huán)境溫度的影響,傳感器標(biāo)定后采用軟件補(bǔ)償方法。為了減少系統(tǒng)費(fèi)用,前端節(jié)點(diǎn)采用半功能節(jié)點(diǎn)設(shè)備,路由器和協(xié)調(diào)器采用全功能節(jié)點(diǎn)設(shè)備,構(gòu)建mesh網(wǎng)絡(luò)所形成的家庭內(nèi)部報(bào)警系統(tǒng),通過(guò)通用的電話接口連接到外部的公用電話網(wǎng)絡(luò),啟動(dòng)語(yǔ)音模塊進(jìn)行報(bào)警。實(shí)驗(yàn)結(jié)果表明,在2.4 GHz頻率下傳輸,有墻等障礙物的情況下,節(jié)點(diǎn)的傳輸距離大約為35 m,能夠滿足家庭需要,且系統(tǒng)工作穩(wěn)定,但在功耗方面仍需進(jìn)一步改善。 Abstract:  On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol,and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator,constructed alarm system within the family by building mesh network,connected to the external public telephone network through the Common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.

    標(biāo)簽: ZigBee 無(wú)線智能 報(bào)警系統(tǒng)

    上傳時(shí)間: 2013-10-30

    上傳用戶:swaylong

  • 差分電路中單端及混合模式S-參數(shù)的使用

    Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and Common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.

    標(biāo)簽: 差分電路 單端 模式

    上傳時(shí)間: 2014-03-25

    上傳用戶:yyyyyyyyyy

  • MAX338/MAX339的英文數(shù)據(jù)手冊(cè)

      本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè):MAX338, MAX339   8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器   The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a Common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a Common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.   These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.

    標(biāo)簽: MAX 338 339 英文

    上傳時(shí)間: 2013-11-12

    上傳用戶:18711024007

  • 飛思卡爾智能車的舵機(jī)測(cè)試程序

    飛思卡爾智能車的舵機(jī)測(cè)試程序 #include <hidef.h>      /* Common defines and macros */#include <MC9S12XS128.h>     /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void)             {       CLKSEL=0X00;        PLLCTL_PLLON=1;          //鎖相環(huán)電路允許位    SYNR=0x00 | 0x01;        //SYNR=1    REFDV=0x80 | 0x01;          POSTDIV=0x00;            _asm(nop);              _asm(nop);    while(!(CRGFLG_LOCK==1));       CLKSEL_PLLSEL =1;          } void PWM_01(void) {     //舵機(jī)初始化   PWMCTL_CON01=1;    //0和1聯(lián)合成16位PWM;    PWMCAE_CAE1=0;    //選擇輸出模式為左對(duì)齊輸出模式    PWMCNT01 = 0;     //計(jì)數(shù)器清零;    PWMPOL_PPOL1=1;    //先輸出高電平,計(jì)數(shù)到DTY時(shí),反轉(zhuǎn)電平    PWMPRCLK = 0X40;    //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz     PWMSCLA = 0x08;    //對(duì)clock SA 16分頻,pwm clock=clockA/16=1MHz;         PWMCLK_PCLK1 = 1;   //選擇clock SA做時(shí)鐘源    PWMPER01 = 20000;   //周期20ms; 50Hz;    PWMDTY01 = 1500;   //高電平時(shí)間為1.5ms;     PWME_PWME1 = 1;   

    標(biāo)簽: 飛思卡爾智能車 舵機(jī) 測(cè)試程序

    上傳時(shí)間: 2013-11-04

    上傳用戶:狗日的日子

  • XAPP740利用AXI互聯(lián)設(shè)計(jì)高性能視頻系統(tǒng)

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a Common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    標(biāo)簽: XAPP 740 AXI 互聯(lián)

    上傳時(shí)間: 2013-11-23

    上傳用戶:shen_dafa

  • pci e PCB設(shè)計(jì)規(guī)范

    This document provides practical, Common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    標(biāo)簽: pci PCB 設(shè)計(jì)規(guī)范

    上傳時(shí)間: 2014-01-24

    上傳用戶:s363994250

  • 確定任務(wù)參數(shù)的溫度記錄儀

    Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are Common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.

    標(biāo)簽: 參數(shù) 溫度記錄儀

    上傳時(shí)間: 2013-11-16

    上傳用戶:xywhw1

  • 電池組電壓測(cè)量的研究

      Automobiles, aircraft, marine vehicles, uninterruptiblepower supplies and telecom hardware represent areasutilizing series connected battery stacks. These stacksof individual cells may contain many units, reaching potentialsof hundreds of volts. In such systems it is oftendesirable to accurately determine each individual cell’svoltage. Obtaining this information in the presence of thehigh “Common mode” voltage generated by the batterystack is more diffi cult than might be supposed.

    標(biāo)簽: 電池組 電壓 量的研究

    上傳時(shí)間: 2013-10-24

    上傳用戶:kang1923

  • 談集成電路的通用接口

    Abstract: How can an interface change a happy face to a sad face? Engineers have happy faces when an interface works properly.Sad faces indicate failure somewhere. Because interfaces between microprocessors and ICs are simple—even easy—they are oftenignored until interface failure causes sad faces all around. In this article, we discuss a Common SPI error that can be almostimpossible to find in a large system. Links to interface tutorial information are provided for complete information. Noise as a systemissue and ICs to minimize its effects are also described.

    標(biāo)簽: 集成電路 通用接口

    上傳時(shí)間: 2013-11-18

    上傳用戶:zgz317

  • The ICA/BSS algorithms are pure mathematical formulas, powerful, but rather mechanical procedures: T

    The ICA/BSS algorithms are pure mathematical formulas, powerful, but rather mechanical procedures: There is not very much left for the user to do after the machinery has been optimally implemented. The successful and efficient use of the ICALAB strongly depends on a priori knowledge, Common sense and appropriate use of the preprocessing and postprocessing tools. In other words, it is preprocessing of data and postprocessing of models where expertise is truly ne

    標(biāo)簽: mathematical algorithms mechanical procedures

    上傳時(shí)間: 2015-03-31

    上傳用戶:silenthink

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