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HIGH SPEED 8051 μC CORE
- Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2
System Clocks
- Up to 25MIPS Throughput with 25MHz System Clock
- 22 Vectored Interrupt Sources
MEMORY
- 4352 Bytes Internal Data RAM (256 + 4k)
- 64k Bytes In-System Programmable FLASH Program Memory
- External Parallel Data Memory Interface – up to 5Mbytes/sec
DIGITAL PERIPHERALS
- 64 Port I/O; All are 5V tolerant
- Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial
Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with 5 Capture/Compare
Modules
- 5 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC, C, or Clock
- Real-Time Clock Mode using Timer 3 or PCA
SUPPLY VOLTAGE ........................ 2.7V to 3.6V
- Typical Operating Current: 10mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP (64-Pin Version Available)
Temperature Range: –40°C to +85°C
標(biāo)簽：
C8051F020
上傳時間：
2013-10-12
上傳用戶：lalalal
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為解決當(dāng)前計算機(jī)串行通訊接口只有USB，難以滿足舊型號設(shè)備或某些單片機(jī)要求RS232通訊的問題，設(shè)計出兩款RS232/USB電路。采用CH341A與MAX223集成電路芯片構(gòu)建標(biāo)準(zhǔn)9線RS232/USB通用接口轉(zhuǎn)換器，無需編程。采用CH341A與PIC16F877A構(gòu)建單片機(jī)與計算機(jī)之間的USB通訊電路，軟件遵循RS232通訊協(xié)議，硬件進(jìn)行電平轉(zhuǎn)換。實(shí)際使用表明，這兩款產(chǎn)品與計算機(jī)端Windows 操作系統(tǒng)下的串口應(yīng)用程序完全兼容，且通訊過程中無握手失敗現(xiàn)象。
Abstract: To solve the problem that current computer serial communication only with USB interface can not satisfy with the old type equipments or MCU to communicate with RS232， two kinds of RS232/USB circuit were designed.CH341A and MAX223 integrated circuit chips were used to create a standard 9-line RS232/USB universal interface convertor without programme. CH341A and PIC16F877A chips were adopted to build the USB communication circuit between computers and MCU. The software follows RS232 communication protocol， and the hardware converts electrical levels. Actual practices indicate that the two manufactures are Compatible with serial application program of Windows operation system completely，and get avoid of handshake lost.
標(biāo)簽：
341A
341
USB
CH
上傳時間：
2013-11-03
上傳用戶：siying
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The PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dotmatrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has40 outputs, of which 24 are programmable and configurable for the following ratios ofrows/columns: 32¤8, 24¤16, 16¤24 or 8¤32. The PCF8578 can function as a stand-alone LCDcontroller and driver for use in small systems. For larger systems it can be used inconjunction with up to 32 PCF8579s for which it has been optimized. Together these twodevices form a general purpose LCD dot matrix driver chip set, capable of driving displaysof up to 40960 dots. The PCF8578 is Compatible with most microcontrollers andcommunicates via a two-line bidirectional bus (I2C-bus). Communication overhead isminimized by a display RAM with auto-incremented addressing and display bankswitching.
標(biāo)簽：
8578
PCF
LCD
圖形點(diǎn)陣
上傳時間：
2013-10-23
上傳用戶：頂?shù)弥?/p>
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1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL Compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
標(biāo)簽：
2116
PCF
LCD
驅(qū)動器芯片
上傳時間：
2013-11-08
上傳用戶：laozhanshi111
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The bootloader is stored in the internal boot ROM memory (system memory) of STM32devices. It is programmed by ST during production. Its main task is to download theapplication program to the internal Flash memory through one of the available serialperipherals (USART, CAN, USB, etc.). A communication protocol is defined for each serialinterface, with a Compatible command set and sequences
標(biāo)簽：
STM
32
啟動代碼
上傳時間：
2014-09-06
上傳用戶：417313137
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Features• Complete DTMF Receiver• Low power consumption• Internal gain setting amplifier• Adjustable guard time• Central office quality• Power-down mode• Inhibit mode• Backward Compatible withMT8870C/MT8870C-1Applications• Receiver system for British Telecom (BT) orCEPT Spec (MT8870D-1)• Paging systems• Repeater systems/mobile radio• Credit card systems• Remote control• Personal computers• Telephone answering machine
標(biāo)簽：
8870D
8870
DTMF
MT
上傳時間：
2013-11-20
上傳用戶：mpquest
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The PCA9549 provides eight bits of high speed TTL-Compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽：
switch
Octal
9549
with
上傳時間：
2014-11-22
上傳用戶：xcy122677
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The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress Compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
標(biāo)簽：
C-bus
9555
SMBu
PCA
上傳時間：
2013-11-13
上傳用戶：fredguo
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The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus Compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anoutput port register, a configuration register, a polarityinversion register and an I²C/SMBus-Compatible serialinterface.
標(biāo)簽：
SMBus
Port
bit
and
上傳時間：
2013-11-09
上傳用戶：liulinshan2010
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The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin Compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽：
synchronous
Emulating
serial
上傳時間：
2014-01-31
上傳用戶：z1191176801
