The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
標(biāo)簽：
CPLD
264
WP
數(shù)字
上傳時(shí)間：
2013-11-03
上傳用戶：1037540470
