This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
飛思卡爾DDR3 PCB布板說明
標(biāo)簽： Layout_Design DDR
上傳時(shí)間： 2013-11-06
上傳用戶：dumplin9
寶德“四子星”PR2760T服務(wù)器是一款特殊優(yōu)化設(shè)計(jì)、性能卓越、安全可靠的高密度機(jī)架式服務(wù)器產(chǎn)品。完美支持Intel最新5500/5600系列QPI處理器、采用Intel5520芯片組、高速DDR3內(nèi)存及SATA硬盤熱插拔技術(shù)，提供超越期待的高性價(jià)比。
標(biāo)簽： 2760T 2760 PR 服務(wù)器
上傳時(shí)間： 2013-11-04
上傳用戶：米卡
白皮書：采用低成本FPGA實(shí)現(xiàn)高效的低功耗PCIe接口 了解一個(gè)基于DDR3存儲(chǔ)器控制器的真實(shí)PCI Express® （PCIe®） Gen1x4參考設(shè)計(jì)演示高效的Cyclone V FPGA怎樣降低系統(tǒng)總成本，同時(shí)實(shí)現(xiàn)性能和功耗目標(biāo)。點(diǎn)擊馬上下載！
上傳時(shí)間： 2013-10-18
上傳用戶：康郎
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
關(guān)于DDR，DDR2,DDR3和MMC的標(biāo)準(zhǔn)規(guī)范。
標(biāo)簽： DDR
上傳時(shí)間： 2013-11-30
上傳用戶：thesk123
JESD79-3C_DDR3 SDRAM，DDR3最新規(guī)范
上傳時(shí)間： 2021-11-29
上傳用戶：aben
HI3520DV400全套資料（Cadence arregro原理圖+PCB+bom+鏡像軟件），1個(gè)HDMI輸入，1個(gè)HDMI輸出，1個(gè)3.5音頻輸入，1個(gè)3.5音頻輸出。2GB-DDR3，2個(gè)USB2.0,1個(gè)LAN，已經(jīng)調(diào)試通過，固件都已經(jīng)打包好。拿來就可以打板生產(chǎn)，包括原理圖，PCB，u-boot,kernel,rootfs。
標(biāo)簽： hi3520dv400 cadence arregro
上傳時(shí)間： 2021-12-28
上傳用戶：
核心板說明（1）DDR模板：RK3288-LPDDR3P232SD6-V12-20140623HXS（2）適用的平臺(tái)：RK3288；（3）支持的DDR類型：LPDDR3_2PCS*32BIT（4）最大支持容量：4G（2PCS*32BIT）；（5）板層：6 Layer；（6）貼片方式：DDR器件單面貼,其它器件雙面貼；（7）面積：35mm*35mm；
標(biāo)簽： rk3288 DDR3 布線 硬件設(shè)計(jì)
上傳時(shí)間： 2022-02-02
上傳用戶：
10個(gè)Altium Designer經(jīng)典案例，含原理圖+PCB8層板設(shè)計(jì) 飛思卡爾IMX6 4片DDR3 設(shè)計(jì) DSN原理圖+PCB；6層板設(shè)計(jì) 全志H8 VR一體機(jī)設(shè)計(jì) DSN原理圖+PCB；6層板設(shè)計(jì) LPC32X0核心板 SCH+PCB2層板設(shè)計(jì) AT89C52 + RC500 Mifare 讀卡器PCB 和原理圖；2層板設(shè)計(jì) 16進(jìn)11出PLC設(shè)計(jì)資料，含原理圖、PCB、物料單、供應(yīng)商、物料價(jià)格；2層板設(shè)計(jì) 顯示屏板SCH+PCB文件；
標(biāo)簽： Altium Designer AD案例
上傳時(shí)間： 2022-04-09
上傳用戶：jiabin
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