What is Verilog?
➥ Verilog HDL is a Hardware Description Language (HDL)
➥ Verilog HDL allows describe designs at a high level of
abstraction as well as the lower implementation levels
➥ Primary use of HDLs is the simulation of designs
➥ Verilog is a discrete event time simulator
What is VeriWell?
➥ VeriWell is a comprehensive implementation of Verilog HDL
標(biāo)簽：
Verilog
HDL
10149
Description
上傳時間：
2017-02-18
上傳用戶：
