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This DOCUMENT and the associated reference design provide guidance for assigning anddebugging software to or in FLASH memory, specifically for a MicroBlaze™ embeddedprocessor design.
上傳時間： 2013-11-11
上傳用戶：dgann
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this DOCUMENT and the information contained herein and assumes no responsibility for any errors that may appear in this DOCUMENT, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths DOCUMENT or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis DOCUMENT is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標簽： Architecture ExpressTM PCI
上傳時間： 2013-11-03
上傳用戶：gy592333
Silicon Motion, Inc. has made best efforts to ensure that the information contained in this DOCUMENT is accurate andreliable. However, the information is subject to change without notice. No responsibility is assumed by SiliconMotion, Inc. for the use of this information, nor for infringements of patents or other rights of third parties.Copyright NoticeCopyright 2002, Silicon Motion, Inc. All rights reserved. No part of this publication may be reproduced, photocopied,or transmitted in any form, without the prior written consent of Silicon Motion, Inc. Silicon Motion, Inc. reserves theright to make changes to the product specification without reservation and without notice to our users
標簽： GUIDELINES LAYOUT 320 PCB
上傳時間： 2014-12-24
上傳用戶：zhaistone
This DOCUMENT provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this DOCUMENT are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This DOCUMENT is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The DOCUMENT is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
Abstract: This DOCUMENT details the Lakewood (MAXREFDES7#) subsystem reference design, a 3.3V input, ±12V (±15V) output, isolated power supply. The Lakewood reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and two wide input range and adjustable output low-dropout linear regulators (LDOs). Test results and hardware files are included.
標簽： MAXREFDES Lakewood Isolated Output
上傳時間： 2013-11-02
上傳用戶：fengzimili
Abstract: This DOCUMENT details the Riverside (MAXREFDES8#) subsystem reference design, a 3.3V input, 12V (15V) output, isolated power supply. The Riverside reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and one wide input range and adjustable output low-dropout linear regulator (LDO). Test results and hardware files are included.
標簽： Riverside MAXREFDES Isolated Output
上傳時間： 2013-11-16
上傳用戶：會稽劍客
Abstract: This DOCUMENT details the Oceanside (MAXREFDES9#) subsystem reference design, a 3.3V to 15V input,±15V (±12V) output, isolated power supply. The Oceanside design includes a high-efficiency step-up controller, a36V H-bridge transformer driver for isolated supplies, a wide input range, and adjustable output low-dropout linearregulator (LDO). Test results and hardware files are included.
上傳時間： 2013-10-12
上傳用戶：jinyao
This DOCUMENT presents design techniques and reference circuits that power Virtex™-4 FXRocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.When using multiple transceivers, it is sometimes preferred to power them from a switchingpower supply. However, switching power supplies generate noise that affects transceiver
上傳時間： 2013-11-18
上傳用戶：huang111
在航電系統(tǒng)維護過程中，為解決定位故障的效率和降低維修成本等問題，提出了基于ICD（Interface Control DOCUMENT，接口控制文件）的1553B總線的信息監(jiān)控系統(tǒng)模型。該系統(tǒng)運用數(shù)據(jù)采集卡對總線中傳輸?shù)男盘栍袩o失真、偏差等電氣特性進行檢測，并使用1553B通訊卡通過測控軟件LabWindows/CVI編程與ICD數(shù)據(jù)庫的動態(tài)鏈接，實現(xiàn)總線信息的解析和故障的判斷。與傳統(tǒng)的維護過程相比，這種模型能夠從信號的電氣特性以及信息的解析等全方位的去檢測判斷故障的來源，并且能夠廣泛在其他1553B總線系統(tǒng)內擴展應用。驗證表明該監(jiān)控系統(tǒng)可以對總線信息進行快速有效地監(jiān)測分析，能滿足應用需求。 Abstract: In the process of avionics system maintenance， to solve the problems such as improving the efficiency of fast orientation to troubles and reducing maintenance cost， system of 1553B bus information monitor model based on ICD was proposed. The system observed whether the data which transmitted on the bus appear distortion and deviation by using data acquisition card. And using 1553B communication card programming of the measure software LabWindows/CVI and the dynamic linking of ICD database， message analysis and fault estimation could be realized. Compared with traditional maintenance， this model can all-dimensionally detect and analyze the source of faults from both electrical characteristics of the signal and message analysis， and it can be widely applied in the other 1553B system. Experiment shown that this monitor system can effectively detect and analyze the bus message and can meet the application requirements.
標簽： 1553B 總線 信息監(jiān)控
上傳時間： 2013-11-23
上傳用戶：18752787361
Information in this DOCUMENT is subject to change without notice and does notrepresent a commitment on the part of the manufacturer. The software describedin this DOCUMENT is furnished under license agreement or nondisclosureagreement and may be used or copied only in accordance with the terms of theagreement. It is against the law to copy the software on any medium except asspecifically allowed in the license or nondisclosure agreement. The purchasermay make one copy of the software for backup purposes. No part of this manualmay be reproduced or transmitted in any form or by any means, electronic ormechanical, including photocopying, recording, or information storage andretrieval systems, for any purpose other than for the purchaser’s personal use,without written permission.
上傳時間： 2014-12-27
上傳用戶：Tracey
