E-Book of Electric DRIVEs and Power Electronics
標(biāo)簽： Electronics Electric E-Book DRIVEs
上傳時(shí)間： 2017-03-19
上傳用戶：wxhwjf
DRIVEs sata for lap with xp 64
標(biāo)簽： DRIVEs sata with for
上傳時(shí)間： 2017-06-20
上傳用戶：jing911003
I am presenting this novel book on advances and trends in power electronics and motor DRIVEs to the professional community with the expectation that it will be given the same wide and enthusiastic acceptance by practicing engineers, R&D professionals, univer- sity professors, and even graduate students that my other books in this area have. Unlike the traditional books available in the area of power electronics, this book has a unique presentation format that makes it convenient for group presentations that use Microsoft’s PowerPoint software. In fact, a disk is included that has a PowerPoint file on it that is ready for presentation with the core figures. Presentations can also be organized using just selected portions of the book
標(biāo)簽： Electronics Advances DRIVEs Power Motor And
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
The MAX14885E, a 2:2 VGA switch, connects a VGA source to a VGA monitor. To ease direct connection to graphics controllers orthe ASIC, the MAX14885E has two supplies: VCC, a 5V ±5% supply, DRIVEs the VGA side interface; and the VL supply sets the logicswitching thresholds on the digital input pins (EN, S00, S01, S10, S11, SHA, SHB, SVA, and SVB). This application note documentsthe proper sequencing of the VCC and VL power supplies on power-up.
標(biāo)簽： 14885E 14885 MAX VGA
上傳時(shí)間： 2013-10-23
上傳用戶：wuchunzhong
Typical industrial and automotive applications requiremultiple high current, low voltage power supply solutionsto drive everything from disc DRIVEs to microprocessors.For many of these applications, particularly thosethat have size constraints, the LT3501® dual step-downconverter is an attractive solution because it’s compactand inexpensive compared to a 2-chip solution. The dualconverter accommodates a 3V to 25V input voltage rangeand is capable of supplying up to 3A per channel. Thecircuit in Figure 1 produces 3.3V and 1.8V.
標(biāo)簽： 排序 雙通道 降壓轉(zhuǎn)換器
上傳時(shí)間： 2014-12-24
上傳用戶：372825274
Abstract: This article discusses future trends in the design of smartphones and other consumer products. The discussion focuses onthe importance of integration, which saves valuable PCB space and DRIVEs down costs.
標(biāo)簽： 集成 智能手機(jī) 驅(qū)動(dòng)器
上傳時(shí)間： 2014-01-13
上傳用戶：lhw888
winCE msdn講座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard DRIVEs, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上傳時(shí)間： 2013-10-31
上傳用戶：jrsoft
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core DRIVEs the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our customers, we must be able to support alltheir interface requirements. For us to be able to make products for many customers, we mustadopt a modular approach to the design. This modularity is the one issue that DRIVEs the majorproblem of shifting our bits from one modular interface to another.
標(biāo)簽： 150 WP 兆兆 網(wǎng)絡(luò)
上傳時(shí)間： 2013-11-25
上傳用戶：suicone
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core DRIVEs the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
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